Dual Chip Enables on both ports for easy depth expansion
Seamless migration to next-generation dual-port family
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Seamless Migration to Next-Generation Dual-Port
Family
Cypress offers a migration path for all devices in this family to the
next-generation devices in the Dual-Port family with a compatible
footprint. Please contact Cypress Sales for more details.
Table 1. Product Selection Guide
Density
Part Number
Max. Speed (MHz)
Max. Access Time – Clock to Data
(ns)
Typical Operating Current (mA)
Package
1 Mbit
(32K x 36)
CYD01S36V
167
4.0
225
2 Mbit
(64K x 36)
CYD02S36V/36VA
167
4.4
225
4 Mbit
(128K x 36)
CYD04S36V
167
4.0
225
9 Mbit
(256K x 36)
CYD09S36V
167
4.0
270
18 Mbit
(512K x 36)
CYD18S36V
133
5.0
315
256 FBGA
256 FBGA
256 FBGA
256 FBGA
256 FBGA
(17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (23 mm x 23 mm)
Cypress Semiconductor Corporation
Document Number: 38-06076 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised Decenber 09, 2008
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Logic Block Diagram
[1]
FTSEL
L
CONFIG Block
PORTSTD[1:0]
L
CONFIG Block
PORTSTD[1:0]
R
FTSEL
R
DQ [35:0]
L
BE [3:0]
L
CE0
L
CE1
L
OE
L
R/W
L
IO
Control
IO
Control
DQ [35:0]
R
BE [3:0]
R
CE0
R
CE1
R
OE
R
R/W
R
Dual Ported Array
BUSY
L
A [18:0]
L
CNT/MSK
L
ADS
L
CNTEN
L
CNTRST
L
RET
L
CNTINT
L
C
L
WRP
L
Arbitration Logic
BUSY
R
A [18:0]
R
CNT/MSK
R
ADS
R
CNTEN
R
CNTRST
R
RET
R
CNTINT
R
C
R
WRP
R
Address &
Counter Logic
Address &
Counter Logic
Mailboxes
INT
L
INT
R
JTAG
TRST
TMS
TDI
TDO
TCK
READY
L
LowSPD
L
RESET
LOGIC
MRST
READY
R
LowSPD
R
Note
1. 18-Mbit device has 19 address bits, 9-Mbit device has 18 address bits, 4-Mbit device has 17 address bits, 2-Mbit device has 16 address bits, and 1-Mbit device has
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