CY7C1386D
CY7C1387D
18-Mbit (512K x 36/1 Mbit x 18)
Pipelined DCD Sync SRAM
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
• Depth expansion without wait state
• 3.3V core power supply (V
DD
)
• 2.5V/3.3V I/O power supply (V
DDQ)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
•
User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Available in JEDEC-standard lead-free 100-pin TQFP,
lead-free and non lead-free 119-ball BGA package and
165-ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1386D/CY7C1387D SRAM integrates 512K x
36/1M x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE
1
), depth-expansion Chip
Enables (CE
2
and CE
3[2]
), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BW
X
, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
The CY7C1386D/CY7C1387D operates from a +3.3V core
power supply while all outputs operate with a +3.3V or a +2.5V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
2.6
350
70
200 MHz
3.0
300
70
167 MHz
3.4
275
70
Unit
ns
mA
mA
Notes:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. CE
3
and CE
2
are for TQFP and 165 FBGA package only. 119 BGA is offered only in Single Chip Enable.
Cypress Semiconductor Corporation
Document #: 38-05545 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 28, 2006
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