5
PRELIMINARY
CY7C1355V25
CY7C1357V25
256Kx36/512Kx18 Flow-Thru SRAM with NoBL™ Architecture
Features
•
Pin compatible and functionally equivalent to ZBT™
devices
• Supports 133-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Registered inputs for Flow-Through operation
• Byte Write capability
• Common I/O architecture
• Single 2.5V power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
— 10.0 ns (for 80-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP & 119 BGA Packages
• Burst Capability—linear or interleaved burst order
respectively. They are designed specifically to support unlim-
ited true back-to-back Read/Write operations without the in-
sertion of wait states. The CY7C1355V25/CY7C1357V25 is
equipped with the advanced No Bus Latency™ (NoBL™) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature dra-
matically improves the throughput of data through the SRAM,
especially in systems that require frequent Write/Read transi-
tions. The CY7C1355V25/CY7C1357V25 is pin compatible
and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 6.5 ns (133-MHz de-
vice).
Write operations are controlled by the Byte Write Selects
(BWS
a,b,c,d
for
CY7C1355V25
and
BWS
a,b
for
CY7C1357V25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Functional Description
The CY7C1355V25 and CY7C1357V25 are 2.5V, 256K by 36
and 512K by 18 Synchronous-Flow-Through Burst SRAMs,
Logic Block Diagram
CLK
D
Data-In REG.
CE Q
ADV/LD
A
x
CEN
CE
1
CE2
CE3
WE
BWS
x
Mode
CONTROL
and WRITE
LOGIC
256KX36/
512KX18
MEMORY
ARRAY
DQ
x
DP
x
CY7C1355
A
X
DQ
X
DP
X
BWS
X
X = 17:0
X= a, b, c, d
X = a, b, c, d
X = a, b, c, d
CY7C1357
X = 18:0
X = a, b
X = a, b
X = a, b
OE
Selection Guide
7C1355V25-133
7C1357V25-133
Maximum Access Time (ns)
Maximum Operating Current (mA)
Shaded areas contain advance information.
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology.
7C1355V25-117
7C1357V25-117
7.5
280
10
7C1355V25-100
7C1357V25-100
8.5
250
10
7C1355V25-80
7C1357V25-80
10.0
200
10
6.5
Com’l
300
10
Maximum CMOS Standby Current (mA) Com’l
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 10, 2000
PRELIMINARY
Pin Configurations
100-Pin TQFP Packages
CY7C1355V25
CY7C1357V25
A
A
CE
1
CE
2
BWSd
BWSc
BWSb
BWSa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
NC
A
A
A
CE
1
CE
2
NC
NC
BWSb
BWSa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
NC
A
NC
DPb
NC
DQb
DQb
NC
V
DDQ
V
DDQ
V
SS
V
SS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
V
SS
V
SS
V
DDQ
V
DDQ
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DPc
DQc
DQc
V
DDQ
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
V
SS
V
DD
V
DD
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DDQ
DQd
DQd
DPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQb
DQb
DQb
DQb
V
SS
Vss
V
DD
V
DD
V
DD
V
DD
V
SS
NC
DQb
DQa
DQa
DQb
V
DDQ
V
DDQ
V
SS
V
SS
DQa
DQb
DQa
DQb
DQa
DPb
DQa
NC
V
SS
V
SS
V
DDQ
V
DDQ
DQa
NC
DQa
NC
NC
DPa
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DPa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
V
DD
V
DD
NC
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
CY7C1355V25
(256K x 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1357V25
(512K x 18)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A
1
A
0
DNU
DNU
V
SS
V
DD
DNU
DNU
A
A
A
A
A
A
A
MODE
A
A
A
A
A
1
A
0
DNU
DNU
V
SS
V
DD
DNU
DNU
A
A
A
A
A
A
2
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PRELIMINARY
Pin Configurations
(continued)
119-Ball Bump BGA
CY7C1355 (256K x 36) - 7 x 17 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC
NC
V
DDQ
CY7C1355V25
CY7C1357V25
2
A
CE
2
A
DP
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQ
d
DQ
d
DP
d
A
64M
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWS
c
V
SS
NC
V
SS
BWS
d
V
SS
V
SS
V
SS
MODE
A
TDI
4
16M
ADV/LD
V
DD
NC
CE
1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
BWS
b
V
SS
NC
V
SS
BWS
a
V
SS
V
SS
V
SS
V
SS
A
TDO
6
A
CE
3
A
DP
b
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
DP
a
A
32M
DNU
7
V
DDQ
NC
NC
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC
NC
V
DDQ
CY7C1357 (512K x 18) - 7 x 17 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
b
NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQ
b
V
DDQ
DQ
b
NC
NC
64M
V
DDQ
2
A
CE
2
A
NC
DQ
b
NC
DQ
b
NC
V
DD
DQ
b
NC
DQ
b
NC
DP
b
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWS
b
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
TDI
4
16M
ADV/LD
V
DD
NC
CE
1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
32M
TCK
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
BWS
a
V
SS
V
SS
V
SS
V
SS
A
TDO
6
A
CE
3
A
DP
a
NC
DQ
a
NC
DQ
a
V
DD
NC
DQ
a
NC
DQ
a
NC
A
A
DNU
7
V
DDQ
NC
NC
NC
DQ
a
V
DDQ
DQ
a
NC
V
DDQ
DQ
a
NC
V
DDQ
NC
DQ
a
NC
NC
V
DDQ
3
PRELIMINARY
Pin Definitions (100-Pin TQFP)
Name
A0
A1
A
BWS
a
BWS
b
BWS
c
BWS
d
WE
ADV/LD
I/O Type
Input-
Synchronous
Input-
Synchronous
Description
CY7C1355V25
CY7C1357V25
Address Inputs used to select one of the 266,144 address locations. Sampled at the
rising edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWS
a
controls DQ
a
and DP
a
, BWS
b
controls DQ
b
and DP
b
, BWS
c
controls DQ
c
and DP
c
, BWS
d
controls DQ
d
and DP
d
.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load input used to advance the on-chip address counter or load a new ad-
dress. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced.
When LOW, a new address can be loaded into the device for an access. After being
deselected, ADV/LD should be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunc-
tion with CE
2
and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in con-
junction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunc-
tion with CE
1
and CE
2
to select/deselect the device.
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state, and when the device has been dese-
lected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized
by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting
CEN does not deselect the device, CEN can be used to extend the previous cycle when
required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[17:0]
during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE and the internal control logic. When OE is
asserted LOW, the pins can behave as outputs. When HIGH, DQ
a
–DQ
d
are placed in
a three-state condition. The outputs are automatically three-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ
[31:0]
.
During write sequences, DP
a
is controlled by BWS
a
, DP
b
is controlled by BWS
b
, DP
c
is controlled by BWS
c
, and DP
d
is controlled by BWS
d
.
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change states
during operation. When left floating MODE will default HIGH, to an interleaved burst
order.
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the device. Should be connected to ground of the system.
No connects. Reserved for address expansion to 512K depths.
Do Not Use pins. These pins should be left floating.
Input-
Synchronous
Input-
Synchronous
CLK
CE
1
CE
2
CE
3
OE
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN
Input-
Synchronous
DQ
a
DQ
b
DQ
c
DQ
d
I/O-
Synchronous
DP
a
DP
b
DP
c
DP
d
MODE
I/O-
Synchronous
Input
Strap pin
V
DD
V
DDQ
V
SS
NC
DNU
Power Supply
I/O Power
Supply
Ground
-
-
4
PRELIMINARY
Pin Definitions (119 BGA)
Name
A0
A1
A
BWS
a
BWS
b
BWS
c
BWS
d
WE
ADV/LD
I/O Type
Input-
Synchronous
Input-
Synchronous
Description
CY7C1355V25
CY7C1357V25
Address Inputs used to select one of the 266,144 address locations. Sampled at the
rising edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
a
controls DQ
a
and DP
a
, BWS
b
controls DQ
b
and DP
b
, BWS
c
controls DQ
c
and DP
c
, BWS
d
controls DQ
d
and DP
d
.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is ad-
vanced. When LOW, a new address can be loaded into the device for an access. After
being deselected, ADV/LD should be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE
2
and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in con-
junction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE
1
and CE
2
to select/deselect the device.
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state, and when the device has been dese-
lected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized
by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting
CEN does not deselect the device, CEN can be used to extend the previous cycle
when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[x:0]
during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE and the internal control logic. When OE
is asserted LOW, the pins can behave as outputs. When HIGH, DQ
a
–DQ
d
are placed
in a three-state condition. The outputs are automatically three-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ
a
–DQ
d
. During write sequences, DP
a
is controlled by BWS
a
, DP
b
is controlled by
BWS
b
, DP
c
is controlled by BWS
c
, and DP
d
is controlled by BWS
d
.
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change states
during operation. When left floating MODE will default HIGH, to an interleaved burst
order.
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the device. Should be connected to ground of the system.
Input-
Synchronous
Input-
Synchronous
CLK
CE
1
CE
2
CE
3
OE
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN
Input-
Synchronous
DQ
a
DQ
b
DQ
c
DQ
d
I/O-
Synchronous
DP
a
DP
b
DP
c
DP
d
MODE
I/O-
Synchronous
Input
Strap Pin
V
DD
V
DDQ
V
SS
ZZ
Power Supply
I/O Power
Supply
Ground
-
5
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