329
PRELIMINARY
CY7C1361V25
CY7C1363V25
CY7C1365V25
256K x 36/256K x 32/512K x 18 Flowthrough SRAM
Features
• Supports 113-MHz bus operations
• 256K x 36 / 256K x 32 / 512K x 18 common I/O
• Fast clock-to-output times
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
— 10.0 ns (for 80-MHz device)
• Two-bit wrap-around counter supporting either inter-
leaved or linear burst sequences
• Separate processor and controller address strobes
provide direct interface with the processor and external
cache controller
• Synchronous self-timed writes
• Asynchronous output enable
• Single 2.5V Power supply
• JEDEC-standard pinout
• Available as a 100-pin TQFP or 119 BGA
• “ZZ” Sleep Mode option
flowthrough SRAM designed to interface with high-speed mi-
croprocessors with minimal glue logic. Maximum access delay
from the clock rise is 7.5 ns (117-MHz device). A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
The CY7C1361V25/CY7C1365V25/CY7C1363V25 supports
either the interleaved or linear burst sequences, selected by
the MODE input pin. A HIGH selects an interleaved burst se-
quence, while a LOW selects a linear burst sequence. Burst
accesses can be initiated by asserting either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC) at clock rise. Address advancement through the burst
sequence is controlled by the ADV input. Byte write operations
are qualified with the Byte Write Select (BW
a,b,c,d
for
CY7C1361V25/CY7C1365V25 and BW
a,b
for CY7C1363V25)
inputs. A Global Write Enable (GW) overrides all byte write
inputs and writes data to all four bytes. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank se-
lection and output three-state control.
Functional Description
The CY7C1361V25, CY7C1365V25 and CY7C1363V25 are
2.5V, 256K x 36, 256K x 32 and 512K x 18 synchronous-
Logic Block Diagram
CLK
ADV
A
x
GW
CE
1
CE
2
CE
3
BWE
BW
x
MODE
ADSP
ADSC
ZZ
OE
CONTROL
and WRITE
LOGIC
D
CE
Data-In REG.
Q
256Kx36/
512Kx18
MEMORY
ARRAY
DQ
x
DP
x
A
X
DQ
X
DP
X
BW
X
7C1361/65
A
[17:0]
DQ
a,b,c,d
DP
a,b,c,d
BW
a,b,c,d
7C1363
A
[18:0]
DQ
a,b,c,d
DP
a,b
BW
a,b
Selection Guide
7C1361-133
7C1365-133
7C1363-133
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Shaded areas contain advance information.
7C1361-117
7C1365-117
7C1363-117
7.5
300
10
7C1361-100
7C1365-100
7C1363-100
8.5
260
10
7C1361-80
7C1365-80
7C1363-80
10.0
210
10
6.5
Commercial
350
10
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
• 408-943-2600
October 23, 2000
PRELIMINARY
Pin Definitions (100-Pin TQFP)
Name
A0
A1
A
BW
a
BW
b
BW
c
BW
d
GW
I/O
Input-
Synchronous
Input-
Synchronous
Description
CY7C1361V25
CY7C1363V25
CY7C1365V25
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are
sampled active. A
[1:0]
feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values on
BW
a,b,c,d
and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
2
to select/deselect the device.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins. OE is masked during the first clock of a
read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it auto-
matically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
LOW, A is captured in the address registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE
1
is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
LOW, A
[x:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Selects burst order. When tied to GND selects linear burst sequence. When tied to
V
DDQ
or left floating selects interleaved burst sequence. This is a strap pin and should
remain static during device operation.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in
the memory location specified by A during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE. When OE is asserted LOW, the pins
behave as outputs. When HIGH, DQ
x
and DP
x
are placed in a three-state condition.
On the CY7C1365 SRAM, these are not connect pins.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in
the memory location specified by A during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE. When OE is asserted LOW, the pins
behave as outputs. When HIGH, DQ
a
–DQ
d
and DP
a
–DP
d
are placed in a three-state
condition.
Power supply inputs to the core of the device. Should be connected to 2.5V power
supply.
BWE
CLK
CE
1
CE
2
CE
3
OE
ADV
ADSP
Input-
Synchronous
Input-
Synchronous
ADSC
Input-
Synchronous
Input-
Static
Input-
Asynchronous
I/O-
Synchronous
MODE
ZZ
NC,DQ
a
NC,DQ
b
NC,DQ
c
NC,DQ
d
DP
a
DP
b
DP
c
DP
d
I/O-
Synchronous
V
DD
Power Supply
4
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