ADVANCE
INFORMATION
CY7C1471V25
CY7C1473V25
CY7C1475V25
2M x 36/4M x 18/1M x 72 Flow-through
SRAM with NoBL™ Architecture
Features
• Zero Bus Latency™, no dead cycles between write and
read
• Supports 133-MHz bus operations
• 2M × 36/4M × 18/1M × 72 common I/O
• Fast clock-to-output times
— 5.5 ns (for 150-MHz device)
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
• Single 2.5V –5% and +5% power supply V
DD
• Separate V
DDQ
for 2.5V or 1.8V I/O
• Clock Enable (CEN) pin to suspend operation
• Burst Capability—linear or interleaved burst order
• Available in 119-ball bump BGA and 100-pin TQFP
packages (CY7C1471V25 and CY7C1473V25). 209
FBGA package for CY7C1475V25.
Clock Enable (CEN), Byte Write Selects (BWS
a
, BWS
b
,
BWS
c
, BWS
d
, BWS
e
, BWS
f
, BWS
g
, BWS
h
), and read-write
control (WE). BWS
c
and BWS
d
apply to CY7C1471V25 and
CY7C1475V25 only. BWS
e
, BWS
f
, BWS
g
, and BWS
h
apply to
CY7C1475V25 only.
A Clock Enable (CEN) pin allows operation of the
CY7C1471V25, CY7C1473V25, and CY7C1475V25 to be
suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is HIGH, and the internal device registers
hold their previous values.
There are three Chip Enable (CE
1
, CE
2
, CE
3
) pins that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(read or write) will be completed. The data bus will be in
high-impedance state two cycles after chip is deselected or a
write cycle is initiated.
The CY7C1471V25,CY7C1473V25 and CY7C1475V25 have
an on-chip two-bit burst counter. In the burst mode,
CY7C1471V25, CY7C1473V25, and CY7C1475V25 provide
four cycles of data for a single address presented to the
SRAM. The order of the burst sequence is defined by the
MODE input pin. The MODE pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load
a new external address (ADV/LD = LOW) or increment the
internal burst counter (ADV/LD = HIGH).
Output Enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the
outputs at any given time. ZZ may be tied to LOW if it is not
used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Functional Description
The CY7C1471V25, CY7C1473V25, and CY7C1475V25
SRAMs are designed to eliminate dead cycles when transi-
tions from Read to Write or vice versa. These SRAMs are
optimized for 100 percent bus utilization and achieves Zero
Bus Latency. They integrate 2,097,152 × 36/4,194,304 ×
18/1,048,576 × 72 SRAM cells, respectively, with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. The Synchronous Burst SRAM family
employs high-speed, low-power CMOS designs using
advanced single layer polysilicon, three-layer metal
technology. Each memory cell consists of six transistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE
1
, CE
2
, and CE
3
), cycle start input (ADV/LD),
Logic Block Diagram
CLK
CE
ADV/LD
A
x
CEN
CE
1
CE2
BWS
X
CE3
WE
CONTROL
and Write
LOGIC
2M × 36/
4M × 18/
1M × 72
MEMORY
ARRAY
D
Data-In REG.
Q
A
X
DQ
X
DP
X
2M × 36
4M × 18
1M × 72
X = 20:0
X = a, b, X= a, b, X = a, b,
c, d
c, d
c, d
BWS
x
Mode
DQ
x
DP
x
X = 21:0 X = a, b X = a, b X = a, b
X = a, b,
X = 19:0 X = a, b, X = a, b,
c,d,e,f,g,h c,d,e,f,g,h
c,d,e,f,g,h
OE
Cypress Semiconductor Corporation
Document #: 38-05287 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 2, 2002
ADVANCE
INFORMATION
Pin Configurations
(continued)
CY7C1475V25 (1M × 72)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQg
DQg
DQg
DQg
DPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DPd
DQd
DQd
DQd
DQd
CY7C1471V25
CY7C1473V25
CY7C1475V25
2
DQg
DQg
DQg
DQg
DPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DPh
DQd
DQd
DQd
DQd
3
A
BWS
c
BWS
h
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CLK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TMS
4
CE
2
BWS
g
BWS
d
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDI
5
A
NC
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
A
A
A
6
ADV/LD
WE
CE
1
OE
V
DD
NC
NC
NC
NC
CEN
NC
NC
NC
ZZ
V
DD
MODE
A
A1
A0
7
A
A
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
A
A
A
8
CE
3
BWS
b
BWS
e
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
9
A
BWS
f
BWS
a
V
SS
V
DDQ
V
SS
V
DDQ
V
SSQ
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TCK
10
DQb
DQb
DQb
DQb
DPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DPa
DQe
DQe
DQe
DQe
11
DQb
DQb
DQb
DQb
DPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DPe
DQe
DQe
DQe
DQe
Pin Definitions
Pin Name
A0
A1
A
BWS
a
BWS
b
BWS
c
BWS
d
BWS
e
BWS
f
BWS
g
BWS
h
WE
ADV/LD
I/O
Input-
Synchronous
Input-
Synchronous
Pin Description
Address Inputs used to select one of the 1048576/2097152/524288 address locations.
Sampled at the rising edge of the CLK.
Byte Write Select Inputs, active LOW.
Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWS
a
controls DQ
a
and DP
a
, BWS
b
controls DQ
b
and DP
b
,
BWS
c
controls DQ
c
and DP
c
, BWS
d
controls DQ
d
and DP
d
. BWS
e
controls DQ
e
and DP
e
, BWS
f
controls DQ
f
and DP
f
, BWS
g
controls DQ
g
and DP
g
, BWS
h
controls DQ
h
and DP
h
.
Input-
Synchronous
Input-
Synchronous
Write Enable Input, active LOW.
Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
Document #: 38-05287 Rev. **
Page 5 of 26
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