C9811
Low EMI Clock Generator for Intel
®
810 Chipset Systems
Preliminary
Product Features
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•
•
•
•
•
•
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•
Intel’s 810 clock solution
3 copies of CPU Clock (CPU[0:1] and CPU_ITP)
9 copies of SDRAM Clock (SDRAM[0:7] and DCLK)
8 copies of PCI clock
2 copies of 3V66 Clock
2 copies of APIC Clock, synchronous to PCI Clock
1 REF Clock
2 USB Clocks (Non SSC)
Power Down Feature
Spread Spectrum Support
2
I C Support for turning off unused clocks
56 Pin SSOP Package
Frequency Table (MHz)
SEL1
0
0
1
1
SEL0
0
1
0
1
CPU
Tristate
66.6
100
SDRAM
Tristate
100
100
Table 1
PCI
Tristate
33.3
33.3
Test mode (see table2)
Note: The following clocks remain fixed frequencies
except in Test Mode.
3V66=66.6MHz, USB/DOT=48MHz, REF=14.318MHz
and IOAPIC=16.6 or 33.3MHz, depending on power up
selection.
Block Diagram
XIN
36pF
X
B
U
F
300K
36pF
VDD
1
REF
Pin Configuration
REF
VDD
XIN
XOUT
VSS
VSS
3V660
3V661
VDD
VDD
PCI0_ICH
PCI1
PCI2
VSS
PCI3
PCI4
VSS
PCI5
PCI6
PCI7
VDD
VDDA
VSSA
VSS
USB0
USB1
VDD
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VSS
IOAPIC0
IOAPIC1
VDDI
CPU0
VDDC
CPU1
CPU2_ITP
VSS
VSS
SDRAM0
SDRAM1
VDD
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDD
SDRAM6
SDRAM7
VSS
DCLK
VDD
PD#
SCLK
SDATA
SEL1
XOUT
VDDI
apic
2
VDDC
cpu
Rin
SCLK
SDATA
SEL1
SEL0
PD#
i2c-clk
i2c-data
s1
s0
pwr_dwn#
66m
2
VDD
pci
PLL1
Rin
PD#
i2c-clk
i2c-data
PLL2
48
1
8
VDD
USB (0:1)
PCI(0:7)
sdram
9
VDD
3V66(0:1)
VDDS
SDRAM(0:7), DCLK
3
CPU(0:2)
IOAPIC(0:1)
C
9
8
1
1
Fig.1
INTERNATIONAL MICROCIRCUITS, INC.
525 LOS COCHES ST., MILPITAS, CA 95035, USA
TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
6/28/1999
Page 1 of 16
C9811
Low EMI Clock Generator for Intel
®
810 Chipset Systems
Preliminary
Pin Description
PIN No.
1
Pin Name
REF
PWR
VDD
I/O
I/O
TYPE
Description
3.3V 14.318 MHz clock output. This pin also serves as the
select strap for IOAPIC clock frequency. If strpped low during
power up, IOAPIC clocks run at PCI (16.6 MHz). This pin has a
50K internal pull-up (+/- 20K).
14.318MHz Crystal input
14.318MHz Crystal output
3.3V PCI clock outputs
3
4
11, 12, 13,
15, 16, 18,
19, 20
7, 8
25, 26
28, 29
30
31
32
34
36, 37, 39,
40, 42, 43,
45, 46
49, 50, 52
54, 55
XIN
XOUT
PCI0/ICH
PCI(1..7)
3V66(0,1)
USB (0:1)
SEL(0,1)
SDATA
SCLK
PD#
DCLK
SDRAM(7..0)
VDD
VDD
VDD
I
O
O
OSC1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDS
O
O
I
I
I
I
O
O
3.3V Fixed 66.6 MHz clock outputs
3.3V Fixed 48 MHz clock outputs
3.3V LVTTL compatible inputs for logic selection. Has an
internal pull-up (Typ. 250KΩ)
I²C compatible SDATA input. Has an internal pull-up (>100KΩ)
I²C compatible SCLK input. Has an internal pull-up (>100KΩ)
3.3V LVTTL compatible input. Device enters powerdown mode
When held LOW. Has an internal pull-up (>100KΩ)
3.3V output running 100MHz
3.3V output running 100MHz. All SDRAM outputs can be turned
2
off through I C.
2.5V Host bus clock outputs. 66 or 100MHz depending on state
of SEL0 and SEL1 pins.
2.5V clock outputs running rising edge synchronous with the
PCI clock frequency. 16.67 MHz or 33.3 MHz dependent on
power up strapping of REF (Pin 1).
3.3V Power Supply
Analog circuitry 3.3V Power Supply
Analog circuitry power supply Ground pins.
2.5V Power Supply’s
Common Ground pins.
CPU(2)_ITP,
CPU(1,0)
IOAPIC(1,0)
VDDC
VDDI
O
O
2, 9, 10, 21,
27
22
23
51, 53
5, 6,14, 17,
24, 35, 41,
47, 48, 56
33, 38, 44
VDD
VDDA
VSSA
VDDC, VDDI
VSS
-
-
-
-
-
P
P
P
P
-
VDDS
-
P
-
3.3V power support for SDRAM clock output drivers.
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
INTERNATIONAL MICROCIRCUITS, INC.
525 LOS COCHES ST., MILPITAS, CA 95035, USA
TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
6/28/1999
Page 2 of 16
C9811
Low EMI Clock Generator for Intel
®
810 Chipset Systems
Preliminary
Test Mode Function
Test Mode Functionality
SEL1
SEL0
CPU
0
1
TCLK/2
SDRAM
TCLK/2
3V66
TCLK/3
PCI
TCLK/6
Table 2
48 MHz
TCLK/2
REF
TCLK
IOAPIC
TCLK/6
Note
:
TCLK is a test clock over driven on the XIN input during test mode.
Power Management Functions
Power Management on this device is controlled by a single pin, PD# (pin32). When PD# is high (default) the device is in
running and all signals are active.
When PD# is asserted (forced) low, the device is in shutdown (or in power down) mode and all power supplies (3.3V and
2.5V except for VDDA/pin 22) may be removed. When in power down, all outputs are synchronously stopped in a low
state (see Fig.2 below), all PLL’s are shut off, and the crystal oscillator is disabled. When the device is shutdown the I²C
function is also disabled.
Power Management Timing
PD#
PCI(1:6)
CPU(1:3)
Fig.2
Power Management Current
PD#, SEL[1..0]
(CPU Clock)
0XX (Power down)
110 (66MHz)
111 (100MHz)
Maximum 2.5 Volt Current
Consumption (VDD2.5 =2.625)
100 µA
70 mA
100 mA
Table 3
Maximum 3.3 Volt Current Consumption
(VDD3.3 = 3.465 V)
200 µA
280 mA
280 mA
When exiting the power down mode, the designer must supply power to the VDD pins first, a minimum of 200mS before releasing
the PD# pin high.
INTERNATIONAL MICROCIRCUITS, INC.
525 LOS COCHES ST., MILPITAS, CA 95035, USA
TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
6/28/1999
Page 3 of 16
C9811
Low EMI Clock Generator for Intel
®
810 Chipset Systems
Preliminary
Clock Synchronization and Phase Alignment
This device incorporates IOAPIC clock synchronization. With this feature, the IOAPIC clocks are derived from the CPU
clock. The IOAPIC clock lags the CPU clock by the specified 1.5 to 3.5 nSec. Figure 3 shows the relationship between
the CPU and IOAPIC clocks.
Device Clock Phase Relationships
0nS
10nS
20nS
30nS
40nS
CPU Clock
66MHz
CPU Clock
100MHz
5nS
7.5nS
5nS
2.5nS
Sync
SDRAM Clock
100MHz
3V66 Clock
66MHz
PCI Clock
33MHz
1.5~3.5nS
IOAPIC Clock
33MHz
Fig.3
INTERNATIONAL MICROCIRCUITS, INC.
525 LOS COCHES ST., MILPITAS, CA 95035, USA
TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
6/28/1999
Page 4 of 16
C9811
Low EMI Clock Generator for Intel
®
810 Chipset Systems
Preliminary
Power on Bi-Directional Pins
Power Up Condition:
Pin1 is a Power up bi-directional pin and is used for selecting the host frequency in page 1, table 1. During power-up of
the device, this pin is in input mode (see Fig 4, below), therefore; it is considered input select pins internal to the IC.
After a settling time, the selection data is latch into the internal control register and this pin becomes a clock output.
POWER SUPPLY
RAMP
VDD RAIL
REF / SEL2
(Pin 1)
Hi-Z INPUTS
-
TOGGLE OUTPUTS
SELECT DATA IS LATCHED INTO REGISTER THEN PIN BECOMES A REF CLOCK OUTPUT SIGNAL
Fig.4
Strapping Resistor Options:
The power up bi-directional pins have a large value pull-
up each (250KΩ), therefore, a selection “1” is the
default. If the system uses a slow power supply (over
5mS settling time), then
it is recommended
to use an
external Pull-up (Rup) in order to insure a high
selection. In this case, the designer may choose one of
two configurations, see Fig.5A and B.
Fig. 5A represents an additional pull up resistor 50KΩ
connected from the pin to the power line, which allows a
faster pull to a high level.
If a selection “0” is desired, then a jumper is placed on
JP1 to a 5KΩ resistor as implemented as shown in
Fig.5A. Please note the selection resistors (Rup and
Rdn) are placed before the Damping resistor (Rd)
close to the pin.
Fig. 5B represent a single resistor 10KΩ connected to a
3-way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
IM I C 9 8 1 1
B id ire c tio n a l
V dd
S e e D e s c rip tio n
R up
10K
Rd
Load
JP 1
JU M P E R
F ig . 5 A
R dn
10K
V dd
JP 2
3 W ay Jum per
3
2
1
R sel
10K
IM I C 9 8 1 1
B id ire c tio n a l
Rd
Load
F ig . 5 B
INTERNATIONAL MICROCIRCUITS, INC.
525 LOS COCHES ST., MILPITAS, CA 95035, USA
TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
6/28/1999
Page 5 of 16
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