CY7C1354CV25-250BZXI datasheet, PDF

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CY7C1354CV25-250BZXI: DescriptionZBT SRAM, 256KX36, 2.8ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165; Categorystorage storage; File Size451KB，28 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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CY7C1354CV25-250BZXI Overview

ZBT SRAM, 256KX36, 2.8ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165

CY7C1354CV25-250BZXI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	2.8 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	250 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	15 mm
memory density	9437184 bit
Memory IC Type	ZBT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.04 A
Minimum standby current	2.38 V
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	13 mm
Base Number Matches	1

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CY7C1354CV25

CY7C1356CV25

9-Mbit (256K x 36/512K x 18)

Pipelined SRAM with NoBL™ Architecture

Features

• Pin-compatible with and functionally equivalent to

ZBT™

• Supports 250-MHz bus operations with zero wait states

• Available speed grades are 250, 200, and 166 MHz

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• Single 2.5V power supply (V

)

• Fast clock-to-output times

— 2.8 ns (for 250-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Available in lead-free 100-Pin TQFP package, lead-free

and non lead-free 119-Ball BGA package and 165-Ball

FBGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

•

Burst capability–linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

[1]

The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x

36 and 512K x 18 Synchronous pipelined burst SRAMs with

No Bus Latency™ (NoBL™) logic, respectively. They are

designed to support unlimited true back-to-back Read/Write

operations with no wait states. The CY7C1354CV25 and

CY7C1356CV25 are equipped with the advanced (NoBL) logic

required to enable consecutive Read/Write operations with

data being transferred on every clock cycle. This feature

dramatically improves the throughput of data in systems that

require frequent Write/Read transitions. The CY7C1354CV25

and CY7C1356CV25 are pin-compatible with and functionally

equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

Write operations are controlled by the Byte Write Selects

(BW

–BW

for CY7C1354CV25 and BW

–BW

for

CY7C1356CV25) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Logic Block Diagram–CY7C1354CV25 (256K x 36)

A0, A1, A

MODE

CLK

CEN

ADDRESS

A1'

A0'

BURST

LOGIC

ADV/LD

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

WRITE

DRIVERS

MEMORY

ARRAY

DQs

DQP

INPUT

CE1

CE2

CE3

READ LOGIC

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note

System Design Guidelines

on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05537 Rev. *H

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised September 14, 2006

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