CY7C1320CV18-300BZXC datasheet, PDF

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CY7C1320CV18-300BZXC: DescriptionDDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165; Categorystorage storage; File Size1MB，28 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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CY7C1320CV18-300BZXC Overview

DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165

CY7C1320CV18-300BZXC Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	300 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	15 mm
memory density	18874368 bit
Memory IC Type	DDR SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.26 A
Minimum standby current	1.7 V
Maximum slew rate	0.6 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	13 mm
Base Number Matches	1

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PRELIMINARY

CY7C1316CV18

CY7C1916CV18

CY7C1318CV18

CY7C1320CV18

18-Mbit DDR-II SRAM 2-Word

Burst Architecture

Features

• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

• 300-MHz clock for high bandwidth

• 2-Word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) @ 300 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Synchronous internally self-timed writes

• DDR-II operates with 1.5 cycle read latency when the

DLL is enabled

• Operates like a DDR-I device with 1 cycle read latency

in DLL off mode

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–V

)

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Offered in both lead-free and non lead-free packages

• JTAG 1149.1-compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Functional Description

The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18 and

CY7C1320CV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry

and a 1-bit burst counter. Addresses for Read and Write are

latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K. Read

data is driven on the rising edges of C and C if provided, or on

the rising edge of K and K if C/C are not provided. Each

address location is associated with two 8-bit words in the case

of CY7C1316CV18 and two 9-bit words in the case of

CY7C1916CV18 that burst sequentially into or out of the

device. The burst counter always starts with a “0” internally in

the case of CY7C1316CV18 and CY7C1916CV18. On

CY7C1318CV18 and CY7C1320CV18, the burst counter

takes in the least significant bit of the external address and

bursts two 18-bit words in the case of CY7C1318CV18 and

two 36-bit words in the case of CY7C1320CV18 sequentially

into or out of the device.

Asynchronous inputs include output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need for

separately capturing data from each individual DDR SRAM in

the system design. Output data clocks (C/C) enable maximum

system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Configurations

CY7C1316CV18 – 2M x 8

CY7C1916CV18 – 2M x 9

CY7C1318CV18 – 1M x 18

CY7C1320CV18 – 512K x 36

Selection Guide

300 MHz

Maximum Operating Frequency

Maximum Operating Current

300

600

278 MHz

278

580

250 MHz

250

550

200 MHz

200

500

167 MHz

167

450

Unit

MHz

Cypress Semiconductor Corporation

Document Number: 001-07160 Rev. *B

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised September 20, 2006

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