Freescale Semiconductor
Advance Information
Document Number: MC33879
Rev 7, 8/2008
Configurable Octal Serial Switch
with Open Load Detect Current
Disable
The 33879 device is an 8-output hardware-configurable, high side /
low side switch with 16-bit serial input control. Two of the outputs may
be controlled directly via microprocessor for PWM applications. The
33879 incorporates SMARTMOS technology, with CMOS logic,
bipolar/MOS analog circuitry, and DMOS power MOSFETs. The 33879
controls various inductive, incandescent, or LED loads by directly
interfacing with a microcontroller. The circuit’s innovative monitoring
and protection features include very low standby currents, cascade
fault reporting, internal + 45 V clamp voltage for low-side configuration,
- 20 V high side configuration, output specific diagnostics, and
independent over-temperature protection.
Features
• Designed to operate 5.5V < V
PWR
< 26.5V
• 16-Bit SPI for control and fault reporting, 3.3V / 5.0V compatible
• Outputs are current limited (0.6A to 1.2A) to drive incandescent
lamps
• Output voltage clamp, + 45V (Low Side) and - 20V (High Side)
during inductive switching
• On/Off control of open load detect current (LED application)
• Internal reverse battery protection on V
PWR
• Loss of ground or supply will not energize loads or damage IC
• Maximum 5.0μA I
PWR
standby current at 13V V
PWR
• R
DS(ON)
of 0.75Ω at 25°C typical
• Short-circuit detect and current limit with automatic retry
• Independent over-temperature protection
• Pb-free packaging designated by suffix code EK
VPWR
+5.0 V
33879
33879A
HIGH SIDE/ LOW SIDE SWITCH
DWB SUFFIX EXPOSED PAD
EK SUFFIX (PB-FREE)
98ARL10543D
32-PIN SOICW
ORDERING INFORMATION
Device
MC33879EK/R2
MCZ33879EK/R2
MCZ33879AEK/R2
-40
°
C to 125
°
C
32 SOICW-EP
Temperature
Range (T
A
)
Package
33879
VDD VPWR
EN
DI
SCLK
CS
DO
IN5
IN6
D1
D2
D3
D4
S1
S2
S3
S4
VBAT
MCU
A0
MOSI
SCLK
CS
MISO
PWM1
PWM2
High-Side Drive
M
D5
D6
D7
D8
S5
S6
S7
S8
H-Bridge Configuration
VBAT
VBAT
Low-Side Drive
GND
Figure 1. 33879 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
(Optional Table)
Freescale Part No.
33879
33879A
V
PWR
Supply Voltage
-16 to 40V
-16 to 45V
Reference Location
6, 7, 13
33879
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
VPWR
~50
μA
Internal
Bias
Power Supply
Charge
Pump
Over-voltage
Shutdown/POR
Sleep State
__
CS
SCLK
DI
DO
GND
OV, POR, SLEEP
Typical of all 8 output drivers
TLIM
SPI Bit 0
~50
μA
Enable
SPI Bit 4
Gate
Drive
Control
Current
Limit
+
–
EN
~110 kΩ
SPI and
Interface
Logic
IN5
Open
Load
Detect
Current
~80
μA
D1
D2
D3
D4
D7
D8
S1
S2
S3
S4
S7
S8
Drain
Outputs
IN6
~50
μA
IN5
+
–
+
–
Open/Short
Comparator
~4.0 V Open/Short
Threshold
Source
Outputs
TLIM
Gate
Drive
Control
Current
Limit
+
–
EP
Exposed Pad
Open
Load
Detect
Current
~80
μA
D5
D6
Drain
Outputs
S5
S6
+
+
–
Source
Outputs
–
Open/Short
Comparator
~4.0 V Open/Short
Threshold
Figure 2. 33879 Simplified Internal Block Diagram
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
GND
VDD
S8
NC
D8
S2
D2
NC
NC
S1
D1
D6
S6
IN6
EN
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
GND
25
24
23
22
21
20
19
18
17
DO
VPWR
NC
S7
D7
S4
D4
NC
NC
S3
D3
D5
S5
IN5
CS
DI
Figure 3. 33879 Pin Connections
Table 2. 33879 Pin Definitions
A functional description of each pin can be found in the
Functional Pin Description
section beginning on
page 15.
Pin Number
1
2
Pin Name
GND
VDD
Pin
Function
Ground
Input
Formal Name
Ground
Logic Supply
Voltage
Source Output 8
Not Connected
Drain Output 8
Source Output 2
Drain Output 2
Source Output 1
Drain Output 1
Drain Output 6
Source Output 6
Command Input 6
Enable Input
SPI Clock
Serial Data Input
SPI Chip Select
Command Input 5
Source Output 5
Drain Output 5
Drain Output 3
Digital ground.
Logic supply for SPI interface. With V
DD
low the device will be in Sleep
mode.
Output 8 MOSFET source pin.
No internal connection to this pin.
Output 8 MOSFET drain pin.
Output 2 MOSFET source pin.
Output 2 MOSFET drain pin.
Output 1 MOSFET source pin.
Output 1 MOSFET drain pin.
Output 6 MOSFET drain pin.
Output 6 MOSFET source pin.
PWM direct control input pin for output 6. IN6 is “OR” with SPI bit.
IC Enable. Active high. With EN low, the device is in Sleep mode.
SPI control clock input pin.
SPI control data input pin from MCU to the 33879. Logic [1] activates output.
SPI control chip select input pin from MCU to the 33879. Logic [0] allows
data to be transferred in.
PWM direct control input pin for output 5. IN5 is “OR” with SPI bit.
Output 5 MOSFET source pin.
Output 5 MOSFET drain pin.
Output 3 MOSFET drain pin.
Definition
3
4, 8, 9,
24, 25, 30
5
6
7
10
11
12
13
14
15
16
17
18
19
20
21
22
S8
NC
D8
S2
D2
S1
D1
D6
S6
IN6
EN
SCLK
DI
CS
IN5
S5
D5
D3
Output
No
Connection
Output
Output
Output
Output
Output
Output
Output
Input
Input
Clock
Input
Input
Input
Output
Output
Output
33879
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 2. 33879 Pin Definitions (continued)
A functional description of each pin can be found in the
Functional Pin Description
section beginning on
page 15.
Pin Number
23
26
27
28
29
31
32
33
Pin Name
S3
D4
S4
D7
S7
VPWR
DO
EP
Pin
Function
Output
Output
Output
Output
Output
Input
Output
Ground
Formal Name
Source Output 3
Drain Output 4
Source Output 4
Drain Output 7
Source Output 7
Battery Input
Serial Data Output
Exposed Pad
Output 3 MOSFET source pin.
Output 4 MOSFET drain pin.
Output 4 MOSFET source pin.
Output 7 MOSFET drain pin.
Output 7 MOSFET source pin.
Power supply pin to the 33879. V
PWR
has internal reverse battery
protection.
SPI control data output pin from the 33879 to the MCU. DO = 0 no fault,
DO = 1 specific output has fault.
Device will perform as specified with the Exposed Pad un-terminated
(floating) however, it is recommended that the Exposed Pad be terminated
to pin 1 (GND) and system ground.
Definition
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
京公网安备 11010802033920号
EEWORLD
