PRELIMINARY
CY7C1311V18
CY7C1313V18
CY7C1315V18
18-Mb QDR™-II SRAM 4-Word Burst Architecture
Features
• Separate Independent Read and Write Data Ports
— Supports concurrent transactions
• 250-MHz Clock for High Bandwidth
• Four-word Burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 500 MHz) at 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew
and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high
speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in ×8, ×18, and ×36 configurations
• 1.8V core power supply with HSTL Inputs and Outputs
• 13 × 15 mm 1.0-mm pitch FBGA package, 165-ball (11 ×
15 matrix)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
• On-chip Delay Lock Loop (DLL)
Functional Description
The CY7C1311V18/CY7C1313V18/CY7C1315V18 are 1.8V
Synchronous Pipelined SRAMs, equipped with QDR-II
architecture. QDR-II architecture consists of two separate
ports to access the memory array. The Read port has
dedicated Data Outputs to support Read operations and the
Write Port has dedicated Data Inputs to support Write opera-
tions. QDR-II architecture has separate data inputs and data
outputs to completely eliminate the need to “turn-around” the
data bus required with common I/O devices. Access to each
port is accomplished through a common address bus.
Addresses for Read and Write addresses are latched on
alternate rising edges of the input (K) clock. Accesses to the
QDR-II Read and Write ports are completely independent of
one another. In order to maximize data throughput, both Read
and Write ports are equipped with Double Data Rate (DDR)
interfaces. Each address location is associated with four 8-bit
words (CY7C1311V18) or 18-bit words (CY7C1313V18) or
36-bit words (CY7C1315V18) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K/K and
C/C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1311V18–2M x 8
CY7C1313V18–1M x 18
CY7C1315V18–512K x 36
Logic Block Diagram (CY7C1311V18)
D
[7:0]
8
19
Write Add. Decode
Read Add. Decode
A
(18:0)
Address
Register
Write Write Write Write
Reg
Reg
Reg Reg
Address
Register
19
A
(18:0)
512K x 8 Array
512K x 8 Array
512K x 8 Array
512K x 8 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
Read Data Reg.
32
Control
Logic
16
Reg.
16
Reg.
8
Reg.
CQ
CQ
V
REF
WPS
BWS
[1:0]
8
Q
[7:0]
Cypress Semiconductor Corporation
Document #: 38-05181 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised July 25, 2002
PRELIMINARY
Logic Block Diagram (CY7C1313V18)
D
[17:0]
18
Write Write Write Write
Reg
Reg
Reg Reg
CY7C1311V18
CY7C1313V18
CY7C1315V18
18
Write Add. Decode
Read Add. Decode
A
(17:0)
Address
Register
Address
Register
18
A
(17:0)
256K x 18 Array
256K x 18 Array
256K x 18 Array
256K x 18 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
Read Data Reg.
72
Control
Logic
36
Reg.
36
Reg.
18
Reg.
CQ
CQ
V
REF
WPS
BWS
[1:0]
18
Q
[17:0]
Logic Block Diagram (CY7C1315V18)
D
[35:0]
36
Write Write Write Write
Reg
Reg
Reg Reg
17
Write Add. Decode
Read Add. Decode
A
(16:0)
Address
Register
Address
Register
17
A
(16:0)
128K x 36 Array
128K x 36 Array
128K x 36 Array
128K x 36 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
Read Data Reg.
144
Control
Logic
72
Reg.
72
Reg.
36
Reg.
CQ
CQ
V
REF
WPS
BWS
[3:0]
36 Q
[35:0]
Selection Guide
[1]
300 MHz
Maximum Operating Frequency
Maximum Operating Current
Note:
1. Shaded cells indicate advanced information.
250 MHz
250
TBD
200 MHz
200
TBD
167 MHz
167
TBD
Unit
mH
mA
300
TBD
Document #: 38-05181 Rev. *A
Page 2 of 23
PRELIMINARY
Pin Configurations
CY7C1311V18 (2M × 8)–11 × 15 FBGA
CY7C1311V18
CY7C1313V18
CY7C1315V18
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/72M
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
A
NC
NC
NC
Q4
NC
Q5
V
DDQ
NC
NC
D6
NC
NC
Q7
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
V
SS
/36M
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
CY7C1313V18 (1M × 18)–11 × 15 FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
V
SS
/72M
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
V
SS
/144M NC/36M
Document #: 38-05181 Rev. *A
Page 3 of 23
PRELIMINARY
Pin Configurations
(continued)
CY7C1315V18 (512K × 36)–11 × 15 FBGA
CY7C1311V18
CY7C1313V18
CY7C1315V18
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
A
10
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
V
SS
/288M NC/72M
NC/36M V
SS
/144M
Pin Definitions
Pin Name
D
[x:0]
I/O
Pin Description
Input-
Data input signals, sampled on the rising edge of K and K clocks during valid write opera-
Synchronous
tions.
CY7C1311V18
−
D
[7:0]
CY7C1313V18
−
D
[17:0]
CY7C1315V18
−
D
[35:0]
Input-
Write Port Select, active LOW.
Sampled on the rising edge of the K clock. When asserted active,
Synchronous a write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D
[x:0]
to be ignored.
WPS
BWS
0
, BWS
1
,
Input-
Byte Write Select 0, 1, 2 and 3
−
active LOW.
Sampled on the rising edge of the K and K clocks
BWS
2
, BWS
3
Synchronous during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1311V18
−
BWS
0
controls D
[3:0]
and BWS
1
controls D
[7:4]
.
CY7C1313V18
−
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1315V18
−
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27]
All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select
will cause the corresponding byte of data to be ignored and not written into the device.
A
Input-
Address Inputs.
Sampled on the rising edge of the K clock during active read and write opera-
Synchronous tions. These address inputs are multiplexed for both Read and Write operations. Internally, the
device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1311V18, 1M x 18 (4 arrays
each of 256K x 18) for CY7C1313V18 and 256K x 36 (4 arrays each of 128K x 36) for
CY7C1315V18. Therefore, only 19 address inputs are needed to access the entire memory array
of CY7C1311V18, 18 address inputs for CY7C1313V18 and 17 address inputs for
CY7C1315V18.These inputs are ignored when the appropriate port is deselected.
Document #: 38-05181 Rev. *A
Page 4 of 23
PRELIMINARY
Pin Definitions
(continued)
Pin Name
Q
[x:0]
I/O
Pin Description
CY7C1311V18
CY7C1313V18
CY7C1315V18
Outputs-
Data Output signals.
These pins drive out the requested data during a Read operation. Valid
Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K and
K. when in single clock mode. When the Read port is deselected, Q
[x:0]
are automatically
three-stated.
CY7C1311V18
−
Q
[7:0]
CY7C1313V18
−
Q
[17:0]
CY7C1315V18
−
Q
[35:0]
Input-
Read Port Select, active LOW.
Sampled on the rising edge of Positive Input Clock (K). When
Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
three-stated following the next rising edge of the C clock. Each read access consists of a burst
of four sequential transfers.
Input-
Clock
Input-
Clock
Input-
Clock
Input-
Clock
Echo Clock
Positive Output Clock Input.
C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Negative Output Clock Input.
C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated
on the rising edge of K.
Negative Input Clock Input.
K is used to capture synchronous inputs being presented to the
device and to drive out data through Q
[x:0]
when in single clock mode.
CQ is referenced with respect to C.
This is a free running clock and is synchronized to the
output clock of the QDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
CQ is referenced with respect to C.
This is a free running clock and is synchronized to the
output clock of the QDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
Output Impedance Matching Input.
This input is used to tune the device outputs to the system
data bus impedance. Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternately, this pin can be connected directly to V
DD
, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
DLL Turn Off.
Connecting this pin to ground will turn off the DLL inside the device. The timings
in the DLL turned off operation will be different from those listed in this data sheet. More details
on this operation can be found in the application note, “DLL Operation in the QDR-II.”
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
No connects inside the package.
Can be tied to any voltage level.
Address expansion for 36M.
This is not connected to the die and so can be tied to any voltage
level.
Address expansion for 72M.
This is not connected to the die and so can be tied to any voltage
level.
Address expansion for 72M.
This must be tied LOW on the these devices.
Address expansion for 144M.
This must be tied LOW on the these devices.
Address expansion for 288M.
This must be tied LOW on the these devices.
RPS
C
C
K
K
CQ
CQ
Echo Clock
ZQ
Input
DOFF
Input
TDO
TCK
TDI
TMS
NC
NC/36M
NC/72M
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
V
SS
/72M
V
SS
/144M
V
SS
/288M
Document #: 38-05181 Rev. *A
Page 5 of 23
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