MG84FL54B
Full-Speed USB micro-controller
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General Description ..........................................................................................................4
Features ........................................................................................................................... 5
Block Diagram ..................................................................................................................6
Pin Configurations ............................................................................................................7
4.1. Pin-out for 48-pin Package ......................................................................................7
4.2. Pin Description.........................................................................................................8
Special Function Registers (SFRs)................................................................................. 10
5.1. SFR Mapping.........................................................................................................10
5.2. The Standard 8051 SFRs ...................................................................................... 11
5.3. The Auxiliary SFRs ................................................................................................ 12
Flash Memory Configuration...........................................................................................14
On-chip expanded RAM (XRAM)....................................................................................15
Dual Data Pointer Register (DPTR) ................................................................................ 16
Configurable I/O Ports ....................................................................................................17
9.1. Port Configurations ................................................................................................17
9.1.1. Quasi-bidirectional....................................................................................................18
9.1.2. Open-Drain Output ...................................................................................................18
9.1.3. Input-Only (Hi-Z) .....................................................................................................19
9.1.4. Push-Pull Output .......................................................................................................20
9.2. Maximum Ratings for Port Outputs........................................................................ 20
Three 16-bit Timers ........................................................................................................21
10.1. Timer 0 and Timer 1 ..............................................................................................21
10.1.1. Mode 0: 13-bit Counter.............................................................................................21
10.1.2. Mode 1: 16-bit Counter.............................................................................................22
10.1.3. Mode 2: 8-bit Auto-reload ........................................................................................22
10.1.4. Mode 3: Timer 0 as Two 8-bit Counter ....................................................................23
10.1.5. Programmable Clock Output from Timer 0..............................................................23
10.2. Timer 2 ..................................................................................................................24
10.2.1. Capture Mode (CP) ...................................................................................................25
10.2.2. Auto-Reload Mode (AR) ..........................................................................................26
10.2.3. Baud-Rate Generator Mode (BRG) ..........................................................................28
10.2.4. Programmable Clock Output from Timer 2..............................................................29
Enhanced UART.............................................................................................................30
11.1. Frame Error Detection ...........................................................................................30
11.2. Automatic Address Recognition.............................................................................30
11.3. Baud Rate Setting.................................................................................................. 32
Interrupt .......................................................................................................................... 35
12.1. Two Priority Levels ................................................................................................ 37
12.2. Interrupt System ....................................................................................................38
12.3. Note on Interrupt during ISP/IAP ........................................................................... 38
Additional External Interrupts (INT2 and INT3)............................................................... 39
This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product
without notice.
©
Megawin Technology Co., Ltd. 2008 All rights reserved.
2008/12. version A2
MEGAWIN
14. Keypad Interrupt .............................................................................................................40
15. Wake-up from Power-down Mode ..................................................................................41
15.1. Power-down Wake-up Sources ............................................................................. 41
15.2. Sample Code for Wake-up from Power-down........................................................ 42
16. Serial Peripheral Interface (SPI) ..................................................................................... 43
16.1. Typical SPI Configurations .................................................................................... 45
16.1.1. Single Master & Single Slave ...................................................................................45
16.1.2. Dual Device, where either can be a Master or a Slave .............................................45
16.1.3. Single Master & Multiple Slaves ..............................................................................46
16.2. Configuring the SPI................................................................................................ 47
16.2.1. Additional Considerations for a Slave ......................................................................47
16.2.2. Additional Considerations for a Master ....................................................................47
16.2.3. Mode Change on /SS-pin ..........................................................................................48
16.2.4. No Write Collision ....................................................................................................48
16.2.5. SPI Clock Rate Select ...............................................................................................48
16.3. Data Mode .............................................................................................................49
16.3.1. SPI Slave Transfer Format with CPHA=0................................................................49
16.3.2. SPI Slave Transfer Format with CPHA=1................................................................49
16.3.3. SPI Master Transfer Format with CPHA=0..............................................................50
16.3.4. SPI Master Transfer Format with CPHA=1..............................................................50
17. 2-wire Serial Interface (TWSI) ........................................................................................ 51
17.1. The Special Function Registers for TWSI.............................................................. 52
17.2. Operating Modes ................................................................................................... 54
17.2.1. Master Transmitter Mode..........................................................................................54
17.2.2. Master Receiver Mode ..............................................................................................55
17.2.3. Slave Transmitter Mode............................................................................................55
17.2.4. Slave Receiver Mode ................................................................................................56
17.3. Miscellaneous States.............................................................................................57
17.4. Using the TWSI...................................................................................................... 58
18. One-Time-Enabled Watchdog Timer (WDT)................................................................... 64
18.1. WDT Block Diagram ..............................................................................................64
18.2. WDT During Idle and Power Down ........................................................................ 65
18.3. WDT Automatically Enabled by Hardware ............................................................. 65
18.4. WDT Overflow Period ............................................................................................65
18.5. Sample Code for WDT...........................................................................................66
19. Universal Serial Bus (USB)............................................................................................. 67
19.1. USB Block Diagram ...............................................................................................67
19.2. USB FIFO Management ........................................................................................ 67
19.3. USB Special Function Registers............................................................................ 68
19.3.1. USB SFR Memory Mapping ....................................................................................68
19.3.2. USB SFR Description ...............................................................................................69
20. In-System-Programming (ISP)........................................................................................76
20.1. Description for ISP Operation ................................................................................77
20.2. Demo Program for ISP ..........................................................................................78
21. In-Application-Programming (IAP) ..................................................................................79
21.1. IAP-memory Boundary/Range ............................................................................... 79
21.2. Update the data in the IAP-memory....................................................................... 79
22. System Clock..................................................................................................................80
22.1. Programmable System Clock ................................................................................ 80
22.2. On-chip XTAL Oscillating Driving Control .............................................................. 81
23. Power-On Reset .............................................................................................................82
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MG84FL54B Data Sheet
MEGAWIN
24. Hardware Option.............................................................................................................83
25. Instruction Set................................................................................................................. 85
25.1. Arithmetic Operations ............................................................................................86
25.2. Logic Operations.................................................................................................... 87
25.3. Data Transfer.........................................................................................................88
25.4. Boolean Variable Manipulation .............................................................................. 89
25.5. Program and Machine Control ...............................................................................90
26. Absolute Maximum Rating..............................................................................................91
27. Electrical Characteristics ................................................................................................91
27.1. Global DC Electrical Characteristics ...................................................................... 91
27.2. USB Transceiver Electrical Characteristics ........................................................... 92
28. Field Applications............................................................................................................93
29. Order Information............................................................................................................93
30. Package Dimension........................................................................................................93
31. Revision History.............................................................................................................. 94
MEGAWIN
MG84FL54B Data sheet
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1. General Description
MG84FL54B is an enhanced single-chip 8-bit microcontroller manufactured in an advanced Embedded-Flash
process. The instruction set is fully compatible with that of the 8051. With the enhanced CPU core, the device
needs only 1 to 7 clock cycles to complete an instruction, and thus provides much higher performance than the
standard 8051, which needs 12 to 48 clock cycles to complete an instruction. So, at the same performance as
the standard 8051, the device can operate at a much lower speed and thereby greatly reduce the power
consumption.
The device has on-chip 16KB Flash memory that is parallel programmable (via a universal programmer), In-
System Programmable (via USB DFU). ISP allows the device to alter its own program memory without being
removed from the actual end product under software control. This opens up a range of applications that need
the ability to field update the application firmware. The other important and useful feature, In-Application-
Programming (IAP), provides the device with the ability to save non-volatile data in its Flash memory.
And in addition to the 256 bytes of internal scratch-pad RAM, the device has 576 bytes of on-chip expanded
RAM (XRAM) for the applications that require extra memory. The device has also four 8-bit I/O ports and one 4-
bit I/O ports, three 16-bit timers/counters, a multi-source/two-priority-level/nested interrupt structure, an
enhanced UART input. More important, the added features such as KBI, SPI, TWSI bus and USB1.1 make it a
powerful microcontroller and suitable for wide field applications.
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MG84FL54B Data Sheet
MEGAWIN
2. Features
1-T 8051 CPU Core
16K bytes of on-chip Flash program memory with ISP/IAP function
256 bytes internal scratch-pad RAM and 576 bytes on-chip expanded RAM (XRAM)
Dual DPTR (Data Pointer register)
Four and half configurable I/O ports
Three 16-bits Timers
Enhanced UART
Two-priority-level interrupt structure
Additional external interrupts, INT2 and INT3
Keypad interrupt (P0)
Wake-up from power-down mode
Serial Peripheral Interface (SPI)
2-wire Serial Interface (TWSI)
One-time-enabled Watch-dog Timer (WDT)
Programmable system clock
USB specification 2.0 and 1.1 compliant
- Built in full speed (12Mbps) USB transceiver
- Intel 8X931 like USB control flow
- One 256 bytes FIFO for USB endpoint-shared buffer
Maximum 64 bytes data for EP0 control-in/out buffer
Maximum 64 bytes data for EP1 bulk/interrupt-in buffer
Maximum 64 bytes data for EP2 bulk/interrupt/isochronous-in buffer, it could be configured to two 32
bytes dual-buffer-mode in bulk and isochronous operating.
Maximum 64 bytes data for EP3 bulk/interrupt/isochronous-out buffer, it could be configured to two 32
bytes dual-buffer-mode in bulk and isochronous operating. Additionally, it also can be configured to an
interrupt-in buffer on EP3 function.
- Supports USB suspend/resume and remote wake-up event
- Software-controlled USB connection/disconnection mechanism
- Support USB DFU (Device Firmware Update)
Power saving modes
- Idle mode
- Power-down mode
Operating voltage
- 2.4 ~ 5.5V on VDD_IO, 2.7V ~ 3.6V on VDD_CORE and VDD_PLL, 3.0V~3.6V on VDDA.
- Built-in Low-Voltage Reset circuit.
Operating temperature
- Industrial (-40°C to +85°C)*
Maximum operating frequency
- Up to 24MHz, Industrial range
Flash Quality criterion:
- Flash data endurance: 20K erase/write cycles
- Flash data retention: 100 years under room temperature
2-level code protection: SB (code scrambled) & LOCK (code locked)
Package: LQFP-48
*: Tested by sampling.
MEGAWIN
MG84FL54B Data sheet
5
Analogue and Mixed Signal
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