CARDINAL COMPONENTS
Low Noise Oscillator
•
Tight Frequency
•
High Stability (Low Jitter)
•
Standard Package Options
Part Numbering Example: CC155 C 1 L Z - A5 B6 - 155.52 TS
Series CC155
CC155
C
1
L
Z
A5
B6
155.52
TS
OPERATING TEMP.
SERIES OUTPUT PACKAGE STYLE VOLTAGE ADDED FEATURES
FREQUENCY TRI-STATE
STABILITY
Blank = 5V Blank = Bulk
Blank = 0°C +70°C B6 = ±100 ppm 155.52 MHz TS = Tri-State
CC155 C = CMOS 1 = Full Size
= Tube
A5
= -20°C +70°C BP = ±50 ppm
T = TTL 4 = Half Size
PD=PowerDwn
L = 3.3 V T
+25 ppm
= -40°C +85°C BR =
Z
= Tape and Reel A7
7 = 5X7 Ceramic
8 = PLASTIC SMD
Specifications:
Output Clock Switching Characteristics
T
EST
C
ONDITIONS
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15
0.8V–2.0V, 4.5-5.5 Vdd
0.2–0.8Vdd, 3.0–3.6 Vdd
From power on
PWR_DWN pin
LOW to output Hi-Z
Min
40
40
Typ Max
60
60
0.9
2.4
2
T/2
10
T/2
10
8
70
T+10
15
T+10
15
100
12
100
Unit
%
%
ns
ns
ms
ns
ns
ns
ns
ns
ps
ps
Frequency Range:
155.52 MHz
Duty Cycle:
Available Stability Options:
+100 ppm
TTL @ 1.4 V, 4.5–5.5 Vdd
+50 ppm
CMOS @ Vdd/2, 4.5–5.5 Vdd
+25 ppm
Output Clock Rise/Fall
Input Voltage:
5.0 VDC
+ 5%
3.3 VDC
Operating Temperature
Range Options:
Storage Temperature:
°C
Aging (PPM/Year)
Ta=25C, Vdd=5/3.3V
Output Level:
Packaging:
Tube
0
-20
-40
-55
±5
TTL/CMOS
+70°C
Start Up Time
+70°C
Power Down Delay Time
+85°C
Synchronous
+125 Asynchronous
Output Disable Time
Synchronous
Asynchronous
Output Enable Time
OE pin LOW to output Hi-Z
T = Freq oscillator period
> 1,000,000 SAMPLES
> JEDEC std JESD65
Tape & Reel
Period Jitter: 1
σ
Sigma
(1K / Reel)
Peak to Peak
Operating Conditions:
min max
Vdd
Digital Supply Voltage
C
TTL
Max Cap Load (TTL)
C
CMOS
Max Cap Load (CMOS)
15
P
F
Electrical Characteristics
Input Characteristics (Pin 1):
V
IL
, Low–Level Input Voltage
TO DISABLE OUTPUT
3.0
5.5 V
15
P
F
4.5–5.5V Vdd
3.0–3.6V Vdd
4.5–5.5V Vdd
3.0–3.6V Vdd
V
IN
= 0V
V
IN
=Vdd
3.0V–3.6V Vdd, 8 mA I
OL
4.5V–5.5V Vdd, 16 mA I
OL
4.5V–5.5V Vdd, -16 mA I
OL
2.40
4.5V–5.5V Vdd, -16 mA I
OL
Vdd-0.4
3.0V–3.6V Vdd, -8 mA I
OL
Vdd-0.4
4.5–5.5 Vdd
3.0–3.6 Vdd
10
4.5–5.5 Vdd, V
IN
= 0V
4.5–5.5 Vdd, V
IN
= 0.7V
5.0 Vdd
Output is Tri-Stated
Controlled by pin 1 input
1.1
50
3.0
100
20
2.0
0.7Vdd
0.8
0.2Vdd
V
V
V
V
V
IH
, High–Level Input Voltage
TO ENABLE OUTPUT OR NO CONNECT
I
IL
, Input Low Current
I
IH
, Input High Current
Output Characteristics:
V
OL
, Low–Level Output
V
OHTTL
, Hi-level Output TTL
V
OHCMOS
,
High-level CMOS Voltage
Power Supply Current:
(unloaded)
Standby Current:
Input Pull-Up Resistor
CLKOUT Pull-Down Current
Output Enable /
Power Down Mode
10
5
0.40
0.40
µA
µA
V
V
V
V
V
45
25
50
8.0
200
mA
mA
µA
MΩ
KΩ
µA
Cardinal Components, Inc., 155 Rt. 46 W, Wayne, NJ. 07470 TEL: (973)785-1333 FAX: (973)785-0053
http://www.cardinalxtal.com
E-Mail: cardinal@cardinalxtal.com
Specifications subject to change without notice. Check website for latest updates
CC155-080601B-1953.2
.
CARDINAL COMPONENTS
Low Noise Oscillator
•
Tight Frequency
•
High Stability (Low Jitter)
•
Standard Package Options
Style 1 Full Size 14 Pin Dip
Series CC155
Note: Bypass Vdd to GND with a 0.01
µF
Capacitor
Style 4 Half Size 8 Pin
Style 7 5x7 Ceramic SMD
Style 8 Plastic SMD
•
•
Cardinal Components, Inc., 155 Rt. 46 W, Wayne, NJ. 07470 TEL: (973)785-1333 FAX: (973)785-0053
http://www.cardinalxtal.com
E-Mail: cardinal@cardinalxtal.com
Specifications subject to change without notice. Check website for latest updates
CC155-012201-1963.2
.
PCB Design
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