PRODUCT SPECIFICATION
PE83502
Military Operating Temperature Range
Product Description
The PE83502 is a high performance monolithic CMOS
prescaler with a fixed divide ratio of 4. Its operating
frequency range is 1.5 GHz to 3.5 GHz. The PE83502
operates on a nominal 3 V supply and draws only 12 mA.
It is packaged in a small 8-lead MSOP and is ideal for
microwave PLL synthesis solutions.
The PE83502 is manufactured in Peregrine’s patented
Ultra Thin Silicon (UTSi
) CMOS process, offering the
performance of GaAs with the economy and integration
of conventional CMOS.
3.5 GHz Low Power CMOS
Divide-by-4 Prescaler
Features
•
High-frequency operation:
1.5 GHz to 3.5 GHz
•
Fixed divide ratio of 4
•
Low-power operation: 12 mA
typical @ 3 V across frequency
•
Small package: 8-lead MSOP
•
Low Cost
Figure 1. Functional Schematic Diagram
Figure 2. Package Drawing
3.05
2.85
D
IN
Pre-Amp
Q
D
Q
OUT
8-lead MSOP
5.05
4.75
CLK QB
CLK QB
Output
Buffer
Table 1. Electrical Specifications
(Z
S
= Z
L
= 50
Ω)
2.85V
≤
V
DD
≤
3.15 V; -55° C
≤
T
A
≤
125° C, unless otherwise specified
Parameter
Supply Voltage
Supply Current
Input Frequency (F
IN
)
Input Power (P
IN
)
Conditions
Minimum
2.85
Typical
3.0
13
Maximum
3.15
19
3.5
+10
+10
Units
V
mA
GHz
dBm
dBm
dBm
1.5
1500 MHz
≤
F
in
≤
3200 MHz
3200 MHz < F
in
≤
3500 MHz
-5
0
-5
Output Power
PEREGRINE SEMICONDUCTOR CORP.
|
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Copyright
Peregrine Semiconductor Corp. 2003
Page 1 of 7
PE83502
Product Specification
Figure 3. Pin Configuration
VDD
IN
DEC
GND
1
2
8
7
GND
OUT
GND
GND
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
PE83502
3
4
6
5
Table 2. Pin Descriptions
Pin
No.
1
2
3
Pin
Name
VDD
IN
DEC
Description
Power supply pin. Bypassing is required.
Input signal pin. Should be coupled with a
capacitor (eg 15 pF)
Power supply decoupling pin. Place a
capacitor as close as possible and connect
directly to the ground plane (eg 10 nF and
10 pF).
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
Ground pin.
Ground pin.
Divided frequency output pin. This pin
should be coupled with a capacitor (eg 100
pF).
Ground pin.
Device Functional Considerations
The PE83502 takes an input signal frequency from
1.5 GHz to 3.5 GHz and produces an output signal
frequency one-fourth that of the supplied input. In
order for the prescaler to work properly, several
conditions need to be adhered to. It is crucial that
pin 3 be supplied with a bypass capacitor to
ground. In addition, the input and output signals
(pins 2 & 7, respectively) need to be AC coupled
via an external capacitor as shown in the test
circuit in Figure 7.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance.
4
GND
5
6
7
GND
GND
OUT
8
GND
Table 3. Absolute Maximum Ratings
Symbol
VDD
T
ST
T
OP
VESD
P
INMAX
Parameter/Conditions
Supply voltage
Storage temperature
range
Operating temperature
range
ESD voltage (Human
Body Model)
Maximum input power
Min
-65
-55
Max
4.0
150
125
250
15
Units
V
°C
°C
V
dBm
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/01025~00B
|
UTSi
CMOS RFIC SOLUTIONS
Page 2 of 7
PE83502
Product Specification
Typical Performance Data: V
DD
= 3.0V
Figure 4. Input Sensitivity
Figure 5. Device Current
Figure 6. Output Power
PEREGRINE SEMICONDUCTOR CORP.
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http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 3 of 7
PE83502
Product Specification
Figure 7. Test Circuit Block Diagram
VDD
3 V +/- 0.15 V
+
-
10 pF
1000 pF
1
8
7
100 pF
50 Ω
Spectrum
Analyzer
50 Ω
15 pF
2
PE83502
3
Signal Generator
4
5
6
10 nF
10 pF
Figure 8. High Frequency System Application
The wideband frequency of operation of the
PE83502
makes it an ideal part for use in a DBS downconverter
system.
INPUT FROM
DBS 1
ST
IF
BASEBAND
OUTPUT
BPF
SAW
AGC
FM
DEMOD
DIVIDE-BY-4
PE3293
PE83502
LOW NOISE
PLL SYNTH
LPF
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/01025~00B
|
UTSi
CMOS RFIC SOLUTIONS
Page 4 of 7
PE83502
Product Specification
Figure 10. Evaluation Board Schematic Diagram
J2-7
Figure 11. Evaluation Board Layout
10 pF
1000 pF
VDD
GND
IN
J1
C1
C3
DEC
10 nF
10 pF
GND
OUT
C1
NC
C2
J3
GND
J4
J5
Evaluation Kit Operation
The MSOP Prescaler Evaluation Board was
designed to help customers evaluate the
PE83502
Divide-by-4 Prescaler. On this board, the device
input (pin 2) is connected to connector J1 through a
50
Ω
transmission line. A series capacitor (C3)
provides the necessary DC block for the device
input. It is important to note that the value of this
capacitance will impact the performance of the
device. A value of 15pF was found to be optimal for
this board layout; other applications may require a
different value.
The device output (pin 7) is connected to connector
J3 through a 50
Ω
transmission line. A series
capacitor (C1) provides the necessary DC block for
the device output. Note that this capacitor must be
chosen to have a low impedance at the desired
output frequency the device. The value of 100pF
was chosen to provide a wide operating range for
the evaluation board.
The board is constructed of a two-layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide above
ground plane model with trace width of 0.030”, trace
gaps of 0.007”, dielectric thickness of 0.028”, metal
thickness of 0.0014” and
ε
r
of 4.4. Note that the
predominate mode for these transmission lines is
coplanar waveguide.
J2 provides DC power to the device. Starting from
the lower left pin, the second pin to the right (J2-3)
is connected to the device VDD pin (1). Two
decoupling capacitors (10 pF, 1000 pF) are
included on this trace. It is the responsibility of the
customer to determine proper supply decoupling for
their design application.
The DEC pin (3) must be connected to a low
impedance AC ground for proper device operation.
On the board, two decoupling capacitors (C6 = 10
nF, C4 = 10 pF), located on the back of the board,
perform this function.
Applications Support
If you have a problem with your evaluation kit or if
you have applications questions call (858) 455-0660
and ask for applications support. You may also
contact us by fax or e-mail:
Fax:
(858) 455-0770
E-Mail:
help@peregrine-semi.com
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 5 of 7
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