NAND02GW4B2DZA6E datasheet, PDF

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NAND02GW4B2DZA6E: Description256M X 8 FLASH 1.8V PROM, 25000 ns, PBGA63; Categorystorage storage; File Size2MB，69 Pages; ManufacturerNumonyx ( Micron ); Websitehttps://www.micron.com; Environmental Compliance

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NAND02GW4B2DZA6E Overview

256M X 8 FLASH 1.8V PROM, 25000 ns, PBGA63

NAND02GW4B2DZA6E Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Numonyx ( Micron )
Parts packaging code	BGA
package instruction	TFBGA, BGA63,10X12,32
Contacts	63
Reach Compliance Code	unknow
ECCN code	3A991.B.1.A
Maximum access time	25000 ns
command user interface	YES
Data polling	NO
JESD-30 code	R-PBGA-B63
length	12 mm
memory density	2147483648 bi
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	2K
Number of terminals	63
word count	134217728 words
character code	128000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA63,10X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
page size	1K words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.05 mm
Department size	64K
Maximum standby current	0.00005 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	NO
type	SLC NAND TYPE
width	9.5 mm

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NAND02G-B2D

2-Gbit, 2112-byte/1056-word page

multiplane architecture, 1.8 V or 3 V, NAND flash memories

Preliminary Data

Features

■

High density NAND flash memory

– Up to 2 Gbits of memory array

– Cost-effective solution for mass storage

applications

NAND interface

– x8 or x16 bus width

– Multiplexed address/data

Supply voltage: 1.8 V or 3.0 V device

Page size

– x8 device: (2048 + 64 spare) bytes

– x16 device: (1024 + 32 spare) words

Block size

– x8 device: (128 K + 4 K spare) bytes

– x16 device: (64 K + 2 K spare) words

Multiplane architecture

– Array split into two independent planes

– Program/erase operations can be

performed on both planes at the same time

Page read/program

– Random access: 25 µs (max)

– Sequential access: 25 ns (min)

– Page program time: 200 µs (typ)

– Multiplane page program time (2 pages):

200 µs (typ)

Copy back program with automatic EDC (error

detection code)

Cache read mode

Fast block erase

– Block erase time: 1.5 ms (typ)

– Multiblock erase time (2 blocks): 1.5 ms

(typ)

■

TSOP48 12 x 20 mm (N)

■

FBGA

VFBGA63 9.5 x 12 mm (ZA)

■

Status register

Electronic signature

Chip Enable ‘don’t care’

Serial number option

Data protection:

– Hardware program/erase disabled during

power transitions

– Non-volatile protection option

ONFI 1.0 compliant command set

Data integrity

– 100,000 program/erase cycles (with ECC)

– 10 years data retention

ECOPACK

packages

Device summary

Part number

NAND02GR3B2D

NAND02G-B2D

NAND02GW3B2D

NAND02GR4B2D

(1)

NAND02GW4B2D

(1)

■

Table 1.

Reference

1. x 16 organization only available for MCP products.

April 2008

Rev 3

1/69

www.numonyx.com

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

Contents

NAND02G-B2D

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10

3.11

Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1

4.2

4.3

4.4

4.5

4.6

Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1

Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1.1

6.1.2

Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2

Cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2/69

NAND02G-B2D

Contents

6.3

Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.1

6.3.2

Sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Random data input in page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4

6.5

6.6

6.7

6.8

6.9

6.10

6.11

Multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Error detection code (EDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.11.1

6.11.2

6.11.3

6.11.4

6.11.5

Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

P/E/R controller and cache ready/busy bit (SR6) . . . . . . . . . . . . . . . . . 36

P/E/R controller bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SR4, SR3, SR2 and SR1 are reserved . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.12

6.13

6.14

6.15

6.16

Read status enhanced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Read EDC status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.1

8.2

8.3

8.4

8.5

Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 48

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3/69

NAND02G-B2D

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Address insertion (x 8 devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Address insertion (x 16 devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Address definition (x 8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Address definition (x 16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Address definition for EDC units (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Address definition for EDC units (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

EDC status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Electronic signature byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Electronic signature byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Parameter page data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Program erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . . 48

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

DC characteristics (1.8 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

DC characteristics (3 V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

AC Characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 65

VFBGA63 9.5 x 12 mm - 6 x 8 active ball array, 0.80 mm pitch, package mechanical

data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5/69

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