Enhanced
Features
s
Memory Systems Inc.
DM2203/2213 Multibank EDO EDRAM
512Kb x 8 Enhanced Dynamic RAM
Product Specification
8Kbit SRAM Cache Memory for 12ns Random Reads Within Four
Active Pages (Multibank Cache)
s
Fast 4Mbit DRAM Array for 30ns Access to Any New Page
s
Write Posting Register for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
s
5ns Output Enable Access Time Allows Fast Interleaving
s
256-byte Wide DRAM to SRAM Bus for 14.2 Gigabytes/Sec Cache Fill
s
On-chip Cache Hit/Miss Comparators Maintain Cache Coherency
Without the Need for External Cache Control
s
A Hit Pin Outputs Status of On-chip Page Hit/Miss Comparators to
Simplify Control
Output Latch Enable Allows Extended Data Output (EDO) For
Faster System Operation
s
Hidden Precharge Cycles
s
Hidden Refresh Cycles
s
Write-per-bit Option (DM2213) for Parity and Video Applications
s
Extended 64ms Refresh Period for Low Standby Power
s
Standard CMOS/TTL Compatible I/O Levels and +5 Volt Supply
s
Low Profile 300-Mil 44-Pin TSOP-II Package
s
Industrial Temperature Range Option
s
Description
The Enhanced Memory Systems 4Mb EDRAM combines raw
speed with innovative architecture to offer the optimum cost-
performance solution for high performance local or main memory in
computer and embedded control systems. In most high speed
applications, zero-wait-state operation can be achieved without
secondary SRAM cache for system clock speeds of up to 83MHz
without interleaving or 132MHz with two-way interleaving. The
EDRAM outperforms conventional SRAM cache plus DRAM or
synchronous DRAM memory systems by minimizing wait states on
initial reads (hit or miss) and by eliminating writeback delays.
Architectural similarity with JEDEC DRAMs allows a single memory
controller design to support either slow JEDEC DRAMs or high speed
EDRAMs. A system designed in this manner can provide a simple
upgrade path to higher system performance.
The 512K x 8 EDRAM has the same control and address interface
as Enhanced’s 4M x 1 and 1M x 4 EDRAM products so that EDRAMs
of different organizations can be supported with the same controller
design. The 512K x 8 EDRAM implements the following additional
features which can be supported on new designs:
s
A controllable output latch provides an extended data out (EDO)
mode.
s
Cache size is increased from 2Kbits to 8Kbits. The 8Kbit cache is
organized as four 256 x 8 direct mapped row registers.
s
A hit pin is provided to tell the memory controller when a hit
occurs to one of the on-chip cache row registers.
Architecture
The EDRAM architecture has a simple integrated SRAM cache
which allows it to operate much like a page mode or static column
DRAM.
Functional Diagram
/CAL
Column
Address
Latch
/HIT
A
0
- A
7
Column Decoder
Pin Configuration
V
CC
/F
V
SS
DQ
0
V
CC
DQ
1
DQ
2
V
SS
DQ
3
QLE
V
CC
/G
DQ
4
V
SS
DQ
5
DQ
6
V
CC
DQ
7
V
SS
NC
NC
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
W/R
/S
A
10
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
/RE
/CAL
V
CC
A
3
A
2
A
1
A
0
/WE
NC
/HIT
V
SS
4 - 9 Bit
Comparators
4 - 256 X 8 Cache Pages
(Row Registers)
QLE
Sense Amps
& Column Write Select
/G
I/O
Control
and
Data
Latches
Row Decoder
Memory
Array
(2048 X 256 X 8)
A
0
- A
10
4 - Last Row
Read Address
Latches
DQ
0
- DQ
7
/S
/WE
Row
Address
Latch
/F
W/R
/RE
Row Adress
and
Refresh
Control
A
0
- A
9
Refresh
Counter
V
CC
V
SS
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
© 1996 Enhanced Memory Systems Inc.
1850 Ramtron Drive, Colorado Springs, CO
Telephone
(800) 545-DRAM;
Fax
(719) 488-9095; http://www.csn.net/ramtron/enhanced
80921
38-2105-001
The EDRAM’s SRAM cache is integrated into the DRAM array
as tightly coupled row registers. The 512K x 8 EDRAM has a total of
four independent DRAM memory banks each with its own 256 x 8
SRAM row register. Memory reads always occur from the cache
row register of one of these banks as specified by row address bits
A
8
and A
9
(bank select). When the internal comparator detects that
the row address matches the last row read from any of the four
DRAM banks (page hit), the SRAM is accessed and data is available
on the output pins in 12ns from column address input. The /HIT
pin is driven low during a page hit to signify to the DRAM control
logic that data is available early. Subsequent reads within the page
(burst reads or random reads) can continue at 12ns cycle time.
When the row address does not match the last row read from any
of the four DRAM banks (page miss), the new DRAM row is
accessed and loaded into the appropriate SRAM row register and
data is available on the output pins all within 30ns from row
enable. In this case, the /HIT pin is driven high to signify to the
control logic that data is available later. Subsequent reads within
the page (burst reads or random reads) can continue at 12ns cycle
time. During either read hit or read miss operations, a user
controllable on-chip output data latch can be used to extend data
output time to allow use of the full 83Mbyte/second bandwidth.
Since reads occur from the SRAM cache, the DRAM precharge
can occur during burst reads. This eliminates the precharge time
delay suffered by other DRAMs and SDRAMs when accessing a new
page. The EDRAM has an independent on-chip refresh counter and
dedicated refresh control pin to allow the DRAM array to be
refreshed concurrently with cache read operations (hidden refresh).
During EDRAM read accesses, data can be accessed in either
static column or page mode depending upon the operation of the
/CAL input. If /CAL is held high, new data is accessed with each new
column address (static column mode). If /CAL is brought low
during a read access, the column address is latched and new data
will not be accessed until both the column address is changed and
/CAL is brought high (page mode). A dedicated output enable (/G)
with 5ns access time allows high speed two-way interleave without
an external multiplexer.
Memory writes are posted to the input data latch and directed
to the DRAM array. During a write hit, the on-chip address
comparator activates a parallel write path to the SRAM cache to
maintain coherency. Random or page mode writes can be posted
5ns after column address and data are available. The EDRAM
allows 12ns page mode cycle time for both write hits and write
misses. Memory writes do not affect the contents of the cache row
Four Bank Cache Architecture
HIT0
HIT1
HIT2
HIT3
Bank 3
Bank 2
Bank 1
Bank 0
/HIT
Row Address Latch
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA
0-10
Column Address Latch
CA
0-7
1M Array
1M Array
1M Array
1M Array
D
0-7
A
0-10
Data-In
Latch
256 x 8
Cache
Bank 0
CA
0-7
256 x 8
Cache
Bank 1
256 x 8
Cache
Bank 2
256 x 8
Cache
Bank 3
(0,0)
RA
8
, RA
9
(0,1)
(1,0)
(1,1)
1 of 4 Selector
CAL
QLE
Data-Out
Latch
G
S
Q
0-7
2-36
register except during a cache hit. Since the DRAM array can be
written to at SRAM speeds, there is no need for complex writeback
schemes.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior performance over standard slow 4Mb DRAMs.
By eliminating the need for SRAMs and cache controllers, system
cost, board space, and power can all be reduced.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
LRR address latch for the bank specified by row address bits A
8-9
(LRR: a 9-bit row address latch for each internal DRAM bank
which is reloaded on each /RE active read miss cycle). If the row
address does not match the LRR, the requested data is not in SRAM
cache and a new row is fetched from the DRAM. The EDRAM will
load the new row data into the SRAM cache and update the LRR
latch. The data at the specified column address is available at the
output pins at the greater of times t
RAC
, t
AC
, and t
GQV
. The /HIT
output is driven high at time t
HV
after /RE to indicate the longer
EDRAM Basic Operating Modes
access time to the external control logic. /RE may be brought high
The EDRAM operating modes are specified in the table below. after time t since the new row data is safely latched into SRAM
RE
cache. This allows the EDRAM to precharge the DRAM array while
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss data is accessed from SRAM cache. Additional locations within the
currently active page may be accessed by providing new column
to any of the four pages of data contained in the SRAM cache row
addresses to the multiplex address inputs. New data is available at
registers. There are four cache row registers, one for each of the
the output at time t
AC
after each column address change in static
four banks of DRAM. These registers are specified by the bank
select row address bits A
8
and A
9
. The contents of these cache row column mode. During any read cycle, it is possible to operate in
registers is always equal to the last row that was read from each of either static column mode with /CAL=high or page mode with /CAL
clocked to latch the column address. In page mode, data valid time
the four internal DRAM banks (as modified by any write hit data). is determined by either t and t .
AC
CQV
DRAM Read Hit
DRAM Write Hit
A DRAM read request is initiated by clocking /RE with W/R low
A DRAM write request is initiated by clocking /RE while W/R,
and /F high. The EDRAM will compare the new row address to the /CAL, /WE, and /F are high. The EDRAM will compare the new row
last row read address latch for the bank specified by row address
address to the LRR address latch for the bank specified by row
bits A
8-9
(LRR: a 9-bit row address latch for each internal DRAM
address bits A
8-9
(LRR: a 9-bit row address latch for each internal
bank which is reloaded on each /RE active read miss cycle). If the DRAM bank which is reloaded on each /RE active read miss cycle).
row address matches the LRR, the requested data is already in the If the row address matches the LRR, the EDRAM will write data to
SRAM cache and no DRAM memory reference is initiated. The data both the DRAM page in the appropriate bank and its corresponding
specified by the row and column address is available at the output SRAM cache simultaneously to maintain coherency. The write
pins at the greater of times t
AC
or t
GQV
. The /HIT output is driven
address and data are posted to the DRAM as soon as the column
low at time t
HV
after /RE to indicate the shorter access time to the
address is latched by bringing /CAL low and the write data is latched
external control logic. Since no DRAM activity is initiated, /RE can by bringing /WE low (both /CAL and /WE must be high when
The EDRAM is designed to provide optimum memory
performance with high speed microprocessors. As a result, it is
possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM
to hide precharge and refresh operation during reads and
maximize hit rate by maintaining page cache contents during write
operations even if data is written to another memory page. These
capabilities, in conjunction with the faster basic DRAM and cache
speeds of the EDRAM, minimize processor wait states.
Functional Description
be brought high after time t
RE1
, and a shorter precharge time, t
RP1
,
is required. Additional locations within the currently active page
may be accessed concurrently with precharge by providing new
column addresses to the multiplex address inputs. New data is
available at the output at time t
AC
after each column address change
in static column mode. During any read cycle, it is possible to
operate in either static column mode with /CAL=high or page
mode with /CAL clocked to latch the column address. In page
mode, data valid time is determined by either t
AC
and t
CQV
.
EDRAM Basic Operating Modes
Function
Read Hit
Read Miss
Write Hit
Write Miss
Internal Refresh
Low Power Standby
Unallowed Mode
/S
L
L
L
L
X
H
H
/RE
↓
↓
↓
↓
↓
H
L
W/R
L
L
H
H
X
X
X
/F
H
H
H
H
L
X
H
A
0-10
Row = LRR
Row
≠
LRR
Row = LRR
Row
≠
LRR
X
X
X
1mA Standby Current
Comment
No DRAM Reference, Data in Cache
DRAM Row to Cache
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
H = High; L = Low; X = Don’t Care; Ø = High-to-Low Transition; LRR = Last Row Read
2-37
initiating the write cycle with the falling edge of /RE). The write
address and data can be latched very quickly after the fall of /RE
(t
RAH
+ t
ASC
for the column address and t
DS
for the data). During a
write burst sequence, the second write data can be posted at time
t
RSW
after /RE. Subsequent writes within a page can occur with write
cycle time t
PC
. With /G enabled and /WE disabled, read operations
may be performed while /RE is activated in write hit mode. This
allows read-modify-write, write-verify, or random read-write
sequences within the page with 12ns cycle times. During a write hit
sequence, the /HIT output is driven low. At the end of any write
sequence (after /CAL and /WE are brought high and t
RE
is satisfied),
/RE can be brought high to precharge the memory. Cache reads can
be performed concurrently with precharge (see “/RE Inactive
Operation”). When /RE is inactive, the cache reads will occur from
the page accessed during the last /RE active read cycle. During write
sequences, a write operation is not performed unless both /CAL and
/WE are low. As a result, the /CAL input can be used as a byte write
select in multi-chip systems.
DRAM Write Miss
A DRAM write request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified for row
address bits A
8-9
(LRR: a 9-bit row address latch for each internal
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address does not match any of the LRRs, the EDRAM will
write data to the DRAM page in the appropriate bank and the
contents of the current cache is not modified. The write address and
data are posted to the DRAM as soon as the column address is
latched by bringing /CAL low and the write data is latched by
bringing /WE low (both /CAL and /WE must be high when initiating
the write cycle with the falling edge of /RE). The write address and
data can be latched very quickly after the fall of /RE (t
RAH
+ t
ASC
for
the column address and t
DS
for the data). During a write burst
sequence, the second write data can be posted at time t
RSW
after
/RE. Subsequent writes within a page can occur with write cycle
time t
PC
. During a write miss sequence, the /HIT output is driven
high, cache reads are inhibited, and the output buffers are disabled
(independently of /G) until time t
WRR
after /RE goes high. At the end
of a write sequence (after /CAL and /WE are brought high and t
RE
is
satisfied), /RE can be brought high to precharge the memory. Cache
reads can be performed concurrently with the precharge (see “/RE
Inactive Operation”). When /RE is inactive, the cache reads will
occur from the page accessed during the last /RE active read cycle.
During write sequences, a write operation is not performed unless
both /CAL and /WE are low. As a result, /CAL can be used as a byte
write select in multi-chip systems.
capable of fast hit/miss comparison. In this case, the controller can
avoid the time required to perform row/column multiplexing on hit
cycles.
Function
Cache Read (Static Column)
Cache Read (Page Mode)
/S
L
L
/G
L
L
/CAL
H
¤
A
0-7
Col Adr
Col Adr
EDO Mode and Output Latch Enable Operation
The QLE and /CAL inputs can be used to create extended data
output (EDO) mode timings in either static column or page modes.
The 512K x 8 EDRAM has an output latch enable (QLE) that can be
used to extend the data output valid time. The output latch enable
operates as shown in the following table.
When QLE is low, the latch is transparent and the EDRAM
operates identically to the standard 4M x 1 and 1M x 4 EDRAMs.
When /CAL is high during a static column mode read, the QLE input
can be used to latch the output to extend the data output valid time.
QLE can be held high during page mode reads. In this case, the
data outputs are latched while /CAL is high and open when /CAL is
not high.
QLE
L
¤
H
/CAL
X
H
¤
Output Transparent
Comments
Output Latched When QLE=H (Static Column EDO)
Output Latched When /CAL=H (Page Mode EDO)
When output data is latched and /S goes high, data does not go
Hi-Z until /G is disabled or either QLE or /CAL goes low to unlatch
data.
/RE Inactive Operation
Data may be read from the SRAM cache without clocking /RE.
This capability allows the EDRAM to perform cache read
operations during precharge and refresh cycles to minimize wait
states. It is only necessary to select /S and /G and provide the
appropriate column address to read data as shown in the table
below. In this mode of operation, the cache reads will occur from
the page accessed during the last /RE active read cycle. To perform
a cache read in static column mode, /CAL is held high, and the
cache contents at the specified column address will be valid at time
t
AC
after address is stable. To perform a cache read in page mode,
/CAL is clocked to latch the column address. When /RE is inactive,
the hit pin is not driven and is in a high impedance state.
This option is desirable when the external control logic is
Write-Per-Bit Operation
The DM2213 version of the 512Kb x 8 EDRAM offers a write-
per-bit capability which allows single bits of the memory to be
selectively written without altering other bits in the same word. This
capability may be useful for implementing parity or masking data in
video graphics applications. The bits to be written are determined
by a bit mask data word which is placed on the I/O data pins DQ
0-7
prior to clocking /RE. The logic one bits in the mask data select the
bits to be written. As soon as the mask is latched by /RE, the mask
data is removed and write data can be placed on the databus. The
mask is only specified on the /RE transition. During page mode
burst write operations, the same mask is used for all write
operations.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles where /S can be disabled.
/CAL Before /RE Refresh (“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
discussed in the “Reduced Pin Count Operation” section.
2-38
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAM refresh, an /RE only refresh may
be performed using an externally supplied row address. /RE
refresh is performed by executing a
write cycle
(W/R, /G, and /F
are high) where /CAL is not clocked. This is necessary so that the
current cache contents and LRR are not modified by the refresh
operation. All combinations of addresses A
0-9
must be sequenced
every 64ms refresh period. A
10
does not need to be cycled. Read
refresh cycles are not allowed because a DRAM refresh cycle does
not occur when a read refresh address matches the LRR address
latch.
Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
mode, the internal DRAM circuitry is powered down to reduce
standby current to 1mA.
Initialization Cycles
A minimum of eight /RE active initialization cycles (read,
write, or refresh) are required before normal operation is
guaranteed. Following these start-up cycles, two read cycles to
different row addresses must be performed for each of the four
internal banks of DRAM to initialize the internal cache logic. Row
address bits A
8
and A
9
define the four internal DRAM banks.
Unallowed Mode
Read, write, or /RE only refresh operations must not be
performed to unselected memory banks by clocking /RE when /S is
high.
Reduced Pin Count Operation
Although it is desirable to use all EDRAM control pins to
optimize system performance, the interface to the EDRAM may be
simplified to reduce the number of control lines by either tying pins
to ground or by tying one or more control inputs together. The /S
input can be tied to ground if the low power standby mode is not
required. The QLE input can be tied low if output latching is not
required, or it can be tied high if “extended data out” (hyper page
mode) is required. The /HIT output pin is not necessary for device
operation. The /CAL and /F pins can be tied together if hidden refresh
operation is not required. In this case, a CBR refresh (/CAL before
/RE) can be performed by holding the combined input low prior to
/RE. A CBR refresh does not require that a row address be supplied
when /RE is asserted. The timing is identical to /F refresh cycle
timing. The /WE input can be tied to /CAL if independent posting of
column addresses and data are not required during write operations.
In this case, both column address and write data will be latched by
the combined input during writes. The W/R and /G inputs can be tied
together if reads are not required during a write hit cycle. If these
techniques are used, the EDRAM will require only three control lines
for operation (/RE, /CAS [combined /CAL, /F, and /WE], and W/R
[combined W/R and /G]). The simplified control interface still allows
the fast page read/write cycle times, fast random read/ write times,
and hidden precharge functions available with the EDRAM.
operations, /RE can be brought high as soon as data is loaded into
cache to allow early precharge.
Pin Descriptions
/RE — Row Enable
This input is used to initiate DRAM read and write operations
and latch a row address. It is not necessary to clock /RE to read
data from the most currently read SRAM row register. On read
/CAL — Column Address Latch
This input is used to latch the column address and in
combination with /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL
transitions low, it latches the address present while /CAL was high.
/CAL can be toggled when /RE is low or high. However, /CAL must
be high during the high-to-low transition of /RE except for /F
refresh cycles. If QLE is high during a read, /CAL will hold data
output until it transitions low.
W/R — Write/Read
This input along with /F specifies the type of DRAM operation
initiated on the low going edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when /F is low on the
low going edge of /RE.
/WE — Write Enable
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are
low.
/G — Output Enable
This input controls the gating of read data to the output data
pins during read operations.
/S — Chip Select
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in its low power mode. /S
must remain active throughout any read or write operation. With the
exception of /F refresh cycles, /RE should never be clocked when /S
is inactive.
DQ
0-7
— Data Input/Output
These bidirectional data pins are used to read and write data
to the EDRAM. On the DM2213 write-per-bit memory, these pins
are also used to specify the bit mask used during write operations.
A
0-10
— Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The 8-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles.
QLE — Output Latch Enable
This input enables the output latch. When QLE is low, the
output latch is transparent. Data is latched when both /CAL and
QLE are high. This allows output data to be extended during either
static column or page mode read cycles.
/HIT — Hit Pin
This output pin will be driven during /RE active read or write
cycles to indicate the hit/miss status of the cycle.
V
CC
Power Supply
These inputs are connected to the +5 volt power supply.
V
SS
Ground
These inputs are connected to the power supply ground
connection.
2-39
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