POS Dot Character Chip In Glass VFD
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DN202MJ
2 Lines of 20 Characters
11.3mm High Dot Matrix Font
Continuous Vertical Matrix.
High Brightness Blue Green Display
Low Pinout Count
Wide Operating Temperature
This VF glass includes a 2 serial shift register, latched drivers which
connects to the anode and grid electrodes. An external host is required
to provide a multiplexing data stream to refresh the display. The signal
inputs can be connected to the ports of a CMOS microprocessor. The
a.c. filament supply (F1, F2) can be derived from a source of 10KHz to
200KHz. Consult our application notes for further information.
2.0
G1
G20
9.5
50.0
31.0
ROW A
ROW B
A1
A41
B1
B41
A5
Adp
Acom
A45
B5
Bdp
Bcom
B45
15.8
196.4
228.0
11.0
11.2
6.0
3
4
23
8.0
9
212.0
8.0
Dimensions in mm
See full spec for tolerances
INTERFACE EXAMPLE
2.0
PIN OUT
Pin
Sig
1
F1
2
F1
3
F1
4
V
DD2
5
V
DD2
6
V
SS
7
V
SS
8
V
DD1
9
GBLK
10
GLAT
11
GCLK
12
GSIN
Pin
13
14
15
16
17
18
19
20
21
22
23
Sig
GSOUT
SOUT
SIN
CLK
LAT
BLK
NP
NP
F2
F2
F2
ELECTRICAL SPECIFICATION
Parameter
Sym Min
Logic Voltage
V
DD1
4.5
Logic Current
I
DD1
-
Filament Voltage E f
7.7
Filament Current I f
270.0
Display Voltage V
DD2
32.0
Display Current I
DD2
-
Filament Bias
E
K
-
Logic High Input V
IH
V
DD1x0.8
Logic Low Input
V
IL
V
SS
Logic High Input
I
IH
-
Logic Low Input
I
IL
-400
Unit
Condition
V
V
SS
=0V
mA
V
DD1
=5V
Vac
V
DD2
=0V
mAac V
DD2
=0V
V
V
SS
=0V
mA
V
DD2
=42V
V
V
SS
=0V
V
V
SS
=0V
V
V
SS
=0V
V
DD1
=5V
µA
V
DD1
=5V
µA
ENVIRONMENTAL and OPTICAL SPECIFICATION
Parameter
Value
Character Size/Pitch (XxY mm) (5x7 dot) 6.5 x 11.3/9.9 X 14.85
Dot Size/Pitch (XxY mm)
1.1 x 1.4/12.5 x 1.65
Luminance
350 cd/m
2
Min
Colour of Illumination
Blue-Green (505nm)
Operating Temperature
-40°C to +85°C
Storage Temperature
-50°C to +85°C
Operating Humidity (non condensing)
5 to 95% @ 25°C
Typ
5.0
3.0
8.6
300.0
42.0
40.0
9.0
-
-
-
-250
Max
5.5
6.0
9.5
330.0
44.0
60.0
-
V
DD1
+0.7
5.0
-35
PA2
KEY
SCAN
TXD
RXD
PA1
MPU PA0
SCK
MOSI
MISO
BLK
LAT
CLK
SIN
SOUT
V
DD1
5V
0V
D
N
2
0
2
M
J
GBLK
20R
V
DD2
F2
F1 Ef
GLAT
V
SS
GSIN
GCLK
10uF
63V
10K
PSU
Ek
MULTIPLEX TIMING
100µs
G1
G2
Gn
Anode
1-48
A+B
Shift Reg Bit
SIN
CLK
LATCH
BLK
95 96
1 2 3
94 95 96
1 2
<10ms
1. Optical filters can provide additional colours.
2. The power on rise time should be less than 50ms.
3. The 20R resistor at the V
DD2
input is required to prevent current surge during
switching.
4. If scanning of the display stops with V
DD2
applied, the BLK input must be set high
to prevent damage to the display
SHIFT REGISTER ASSIGNMENT
Electrode
GSIN Bit No:
Grid G1-G20
1-20
Not Connected
21-32
Electrode
Dot A1-A45
Dot B1-B45
Not Connected
SIN Bit No:
96-50
48-1
49
INTERFACE TIMING
Parameter
Time
CLK Cycle
200ns min
CLK High
80ns min
CLK Low
80ns min
SIN Setup
40ns min
SIN Hold
30ns min
LAT High
300ns min
CLK then LAT
250ns min
BLK Hold
10µs min
POWER SEQUENCE
V
DD2
42V
CONTACT
Noritake Sales Office Tel N o s
Nagoya Japan: +81 (0 )52-561-9867
Canada: +1-416-291-2946
Chicago USA: +1-847-439-9020
Munchen (D): +49 (0)89-3214-290
Itron UK: +44 (0 )1493 601144
Rest Europe: +49 ( 0)61-0520-9220
www.noritake-itron.com
Subject to change without notice.
Doc Ref: 00944 Iss:5 30NOV99
V
DD1
ON
OFF
5V
NORITAKE ITRON VFD
2 x 20 11.3mm Dot Character
Discrete Device
京公网安备 11010802033920号
EEWORLD
