DY6009BG432EI datasheet, PDF - EEWORLD Datasheet

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DY6009BG432EI: DescriptionField Programmable Gate Array, 256-Cell, CMOS, PBGA432,; CategoryProgrammable logic devices Programmable logic; File Size644KB，64 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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DY6009BG432EI Overview

Field Programmable Gate Array, 256-Cell, CMOS, PBGA432,

DY6009BG432EI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Reach Compliance Code	not_compliant
JESD-30 code	S-PBGA-B432
JESD-609 code	e0
Humidity sensitivity level	3
Number of entries	128
Number of logical units	256
Output times	128
Number of terminals	432
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA432,31X31,50
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
Base Number Matches	1

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DY6000

™

Family

FAST

Field Programmable Gate Array

™

Features

•

Predictable, Fast, Patented Active Repeater™

Architecture

I/O Data-Transfer Rates up to 200MHz

2.7ns I/O Clock-to-Output Time with 10pf Load;

3.2ns with 50pf Load

1.4ns I/O Input Register Setup Time

9,000 to 55,000 Usable Gates

32-Bit Synchronous 8ns-Access, Two-Clock,

Two-Port SRAM in Every Logic Block, to

Support 125MHz FIFOs

Two PLLs for 8MHz-to-200MHz Clock

Multiplication, Division, and Locking with

Programmable Latency

Ten Clock Trees with 200ps Worst-Case Clock

Skew

150ps Worst-Case Pin-to-Pin Skew Between

Registered Logic Outputs to Support Fast Buses

In-System Reprogrammability

Dynamic Single-Block Reconfigurability

TTL, LV-TTL, GTL, and GTLP Interface Levels;

24mA IOL Drive for GTL, 48mA IOL Drive for

GTLP

Up to Nineteen LVDS-Compatible Input Pairs

Up to Nineteen Differential LV-PECL Input Pairs

66MHz, 64-Bit, Zero-Wait-State PCI Soft Core

3.3V Operation with 5V-Tolerant I/O

Hot-Swappability – no System Shutdown

Required When Exchanging Circuit Boards

JTAG (IEEE1149.1) Boundary-Scan

Conformance

Individual Slew-Rate Controls for Each Output

Fully-Automatic Design Implementation Using

DynaTool™

432-Pin EBGA and 240-Pin EQFP Packages

•

Applications Examples

•

Data Communications: Gigabit Ethernet, ATM,

Fibre Channel, Token Ring, SONET – Switching,

Routing, CRC Functions

Telecommunications

High-Speed Graphics

On-the-Fly-Reconfigurable Systems

Servers and Supercomputers

PCI Interfaces

ASIC Emulation

Semiconductor Testers

High-Performance Instrumentation

Medical Imaging Systems

•

Device

DY6009

DY6020

DY6035

DY6055

Gates

9,000

20,000

35,000

55,000

Logic

Blocks

256

576

1,024

1,600

Max User

SRAM Bits

8,192

18,432

32,768

51,200

Flip- ﬂops

768

1,536

2,560

3,840

Clock

Trees

I/O Blocks

128

192

256

320

Table 1: DY6000 Family

DY6000 Family Datasheet Revision 1.1

April 1999

DY6000 - Fast Field Programmable Gate Array

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

DY6000 Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Performance Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

High-Performance Active Repeater Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Top-Level Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Routing Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Input/Output Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

External GTL/GTLP and LV-PECL Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Logic Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Phase-Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Advance Estimates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Configuration Pin Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Reconfiguration and Resetting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Configuration-Related Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Product Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Clock and Set/Reset Buffer Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

I/O Block Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Logic Block Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

432-Pin EBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

240-Pin EQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

432-Pin EBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

240-Pin Thermal Enhanced EQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Sales and Corporate Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Back 3 Pages

Page 2

DY6000 Family Datasheet Revision 1.1

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