DM74AS86J/A+ datasheet, PDF - EEWORLD Datasheet

DM74AS86J/A+: DescriptionIC,LOGIC GATE,QUAD 2-INPUT XOR,AS-TTL,DIP,14PIN,CERAMIC; Categorylogic logic; File Size110KB，2 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

Stay tuned Parametric Compare

DM74AS86J/A+ Overview

IC,LOGIC GATE,QUAD 2-INPUT XOR,AS-TTL,DIP,14PIN,CERAMIC

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	DIP, DIP14,.3
Reach Compliance Code	unknown
JESD-30 code	R-XDIP-T14
JESD-609 code	e0
Logic integrated circuit type	XOR GATE
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Schmitt trigger	NO
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Base Number Matches	1

	DM74AS86J/A+	DM54AS86J/883C	DM54AS86J/883B	DM74AS86N/B+
Description	IC,LOGIC GATE,QUAD 2-INPUT XOR,AS-TTL,DIP,14PIN,CERAMIC	IC,LOGIC GATE,QUAD 2-INPUT XOR,AS-TTL,DIP,14PIN,CERAMIC	IC,LOGIC GATE,QUAD 2-INPUT XOR,AS-TTL,DIP,14PIN,CERAMIC	IC,LOGIC GATE,QUAD 2-INPUT XOR,AS-TTL,DIP,14PIN,PLASTIC
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Reach Compliance Code	unknown	compliant	compliant	unknown
JESD-30 code	R-XDIP-T14	R-XDIP-T14	R-XDIP-T14	R-PDIP-T14
JESD-609 code	e0	e0	e0	e0
Logic integrated circuit type	XOR GATE	XOR GATE	XOR GATE	XOR GATE
Number of terminals	14	14	14	14
Maximum operating temperature	70 °C	125 °C	125 °C	70 °C
Package body material	CERAMIC	CERAMIC	CERAMIC	PLASTIC/EPOXY
encapsulated code	DIP	DIP	DIP	DIP
Encapsulate equivalent code	DIP14,.3	DIP14,.3	DIP14,.3	DIP14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE	IN-LINE
power supply	5 V	5 V	5 V	5 V
Schmitt trigger	NO	NO	NO	NO
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	NO
technology	TTL	TTL	TTL	TTL
Temperature level	COMMERCIAL	MILITARY	MILITARY	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Base Number Matches	1	1	1	1
Certification status	-	Not Qualified	Not Qualified	Not Qualified

Problems with application access to drivers: Hello everyone, what are the two functions SetProcPermissions and MapPtrToProcess used for? Do SetProcPermissions and MapPtrToProcessr have the same function?...; e3e4shine Embedded System

STEVAL-IDB007V1 low voltage and high voltage test: This time we tested the data transmission under voltage limit. From the STEVAL-IDB007V1_datasheet, we can see that the voltage range is 1.2~3.6, compatible with 5v, and the highest input is 6v. From t...; lehuijie ST - Low Power RF

Are fill and copper plating the same on a circuit board?: I have never used fill, can an expert tell me, is fill the same as copper? I heard that copper on the power supply will cause a short circuit on the board, will it be the same with the signal? Is fill...; cyp1982 PCB Design

Please recommend a model!!! Urgent!!! Thank you everyone: I have been using 430 MCU before, and I need to use an ARM chip recently. I need 16-bit AD acquisition and 12 or 16-bit DA acquisition. The actual acquisition speed is at least 8K, and it has an Ether...; 万手11 ARM Technology

Now access the simple web server based on the lwIP protocol stack: I made a simple web server using the LM3S8962 based on the lwIp protocol stack. You should be able to access the development board that is now connected to the router through the following address.Mor...; academic Microcontroller MCU

FPGA - Open Course - Episode 02 - Verilog Implementation of Algorithm - FIR Filter: [color=#808080][font=宋体][size=5]In this open class, Mr. Pan Wenming will explain the Verilog implementation of the FIR filter algorithm. [/size][/font][/color] [color=#808080][font=宋体][size=5]http://w...; njiggih FPGA/CPLD

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components