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SEMICONDUCTOR
TECHNICAL DATA
DSP56ADC16
Technical Information
DSP56ADC16
16-bit Sigma-Delta Analog-to-Digital Converter
Available in a 20 pin
CERDIP package
The DSP56ADC16 is a single chip, linear, 16-bit oversampling analog-to-digital (A/D) converter, providing output
sample rates up to 100 KHz. Third order noise shaping sigma-delta technology is employed utilizing 64 times
oversampling which yields 96 dB dynamic range and 90 dB signal-to-noise ratio for the signal bandwidths from
0 to 45.5 KHz with an in-band ripple of less than 0.001 dB. The DSP56ADC16 is an ideal choice for high perfor-
mance digital audio systems, such as digital audio disks, tapes, and processors as well as voice-bandwidth com-
munication and control applications. It does not require anti-aliasing filters and sample-and-hold circuitry
because they are an inherent part of the sigma-delta technology. Due to the scalable design principles, the ef-
fective output sampling rate can be adjusted from 8 KHz to 100 KHz without losing specified characteristics. The
DSP56ADC16 can easily be interfaced to the DSP56001/2 or other host processors using its flexible serial inter-
face. An output is also provided before the final FIR decimation filter for applications requiring higher speed, low-
er group delay, and only 12-bit accuracy for AC levels. The DSP56ADC16 can also be used with an input
multiplexer at a minimum output sampling interval of 15
µ
s in the comb filter output mode.
DSP56ADC16 Key Features
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16-Bit Output Resolution (96 dB Typical Dynamic Range) at 100 KHz from the FIR Filter
12-Bit Output Resolution (72 dB Typical Dynamic Range) at 400 KHz from the Comb Filter
90 dB Signal-to-Noise Ratio (SNR)
In-Band Ripple: < 0.001 dB
Adjustable Output Sampling Rates:8 KHz to 100 KHz (FIR FIlter)
32 KHz to 400 KHz (Comb Filter)
Maximum Input Sample Rate: 6.4 MHz
Maximum Internal Clock Rate:12.8 MHz
Single +5 V
±
10% Supply
On-chip voltage reference
3.5 Volt p-p full-scale differential inputs
Typical Power consumption: 300 mW at 100 KHz sampling rate
20-Pin CERDIP Package
Single Chip
Linear Phase Analog Front End and Internal Digital Filters
Simple Serial Interface to Host Microprocessors
No-glue Interface to DSP5600x/DSP561xx and Most Other General Purpose DSPs
This document contains information on a new product. Specifications and information herein are subject to change without notice.
©
MOTOROLA INC., 1992
MOTOROLA
December 7, 1992
INTERNAL ARCHITECTURE
The A/D converter is a key component in data acqui-
sition systems, such as those found in digital audio
systems, high-accuracy measurement systems, com-
munications, and digital signal processing systems in
general. High resolution A/D converters have typically
used successive approximation techniques with com-
plicated trimming/calibration or dual-ramp conversion
techniques which require accurate comparators and
expensive sample-and-hold (S/H) circuits to yield
over 15 bits of accuracy. In addition, the anti-aliasing
filter for these A/D converters generally sets severe
limitations on the attainable signal-to-noise ratio and
phase linearity.
The DSP56ADC16 uses an advanced third order sig-
ma delta quantizer to implement an oversampled
noise shaping A/D converter system on a single chip.
By oversampling the input signal, the overall quanti-
zation noise spectrum expands well beyond the fre-
quency band of interest. Third order noise shaping
insures that this expanded noise spectrum contains
very little noise power in the passband. The oversam-
pled signal is lowpass filtered, effectively removing the
out-of-band quantization noise. The lowpass filtering is
then followed by decimation to reduce the output sam-
ple rate commensurate with the frequency band of in-
terest and to increase the resolution. In the
DSP56ADC16, the filtering and decimation are done in
two steps to reduce digital filter complexity. Since the
input signal is oversampled by a factor of 64, the need
for a high order antialiasing filter can be eliminated.
The DSP56ADC16 consists of three major sections: 1)
analog front end (AFE), 2) compensated decimation
digital filters and 3) serial interface, as shown in Figure
1. The AFE consists primarily of three differential
switched-capacitor linear integrators. These highly
stable fully differential integrators perform the noise
shaping function. The decimation digital filter section
consists of a 16:1 decimation comb filter stage fol-
lowed by a 4:1 decimation lowpass/compensation FIR
filter stage which results in a total decimation ratio of
64:1. The frequency response of the decimation digital
filters is described in the “
First and Second Stage
Decimation Digital Filters
” section. The “
Serial Inter-
face
” section provides serial communication to a host
DV
CC
Filter Select
AV
CC
REF Output
Serial Format
V
REF
REF Input
+Analog
Input
-Analog
Input
Analog
Front
End
16:1
Decimation
Comb
Filter
4:1
Decimation
Fir
Filter
Serial Clock Out
Mux
Serial
Interface
Serial Data Out
Frame Sync Out
12.8 MHz
6.4 MHz
6.4 MHz
Frame Sync
Input
Clock Input
(12.8 MHz)
System Timing and Control
AGND
DGND
3.2 MHz
DOE
Figure 1. Internal Block Diagram
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DSP56ADC16
processor. This interface uses three dedicated pins
— serial data output (SDO), frame sync output (FSO),
and serial clock output (SCO). The serial interface for-
mat of operation is pin selectable. The timing dia-
grams for the serial interface are described in the “
AC
Electrical Specifications
” section.
common CLKIN signal is required when using a com-
mon frame sync signal with multiple DSP56ADC16s.
Analog + Input (V
IN+
)
This pin is the A/D converter analog non-inverting in-
put. If an input anti-aliasing filter is used prior to the
V
IN
inputs, high quality polystyrene or equivalent ca-
pacitors must be used in order to meet the published
THD specification. See the connection diagram ex-
ample in Figure 7 for a typical single pole input filter.
The maximum peak-to-peak input signal is a function
of the reference input voltage, V
refin
, which is ex-
pressed as
Maximum input range = 2 * V
refin
- 0.5 Volts p-p
The constant 0.5 Vp-p in the equation above is used
for internal dither circuitry.
SIGNAL DESCRIPTION
The DSP56ADC16 is available in a 20-pin CERDIP
package. The functional pin definitions and their mne-
monics are listed below and shown in Figure 2.
AGND
VIN+
VIN-
CLKIN
FSI
FSEL
SFMT
DV
CC
FSO
SCO
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
REFIN
REFOUT
AV
CC
DGND
DGND
DGND
DGND
DGND
DOE
SDO
DSP56ADC16
Analog - Input (V
IN-
)
This pin is the A/D converter analog inverting input
with the same characteristics as VIN
+
.
Figure 2. DSP56ADC16 Pin Assignment
Reference Input (REFIN)
This pin is the analog reference voltage (V
refin
) ap-
plied to this pin sets the analog input range. Its mag-
nitude sets both the positive and negative full-scale
range. The maximum input is +2.0 volts. Since this in-
put is extremely sensitive to induced noise, reference
input decoupling is suggested to achieve the maxi-
mum performance as shown in Figures 7 and 15. Fail-
ure to decouple may result in a degradation of the
SNR. The output of the DSP56ADC16 is
Clock Input (CLKIN)
This pin accepts the input clock for the
DSP56ADC16. This TTL level compatible input ac-
cepts clock frequencies in the range of 1.0 to 12.8
MHz. The output sample rate is equal to the CLKIN
frequency divided by 128.
Frame Sync Input (FSI)
This active high input is used to start or reset the se-
rial data output and synchronize internal circuits. It is
not a start conversion pulse since the DSP56ADC16
is always converting at a rate of CLKIN/128. FSI is
sampled on the falling edge of CLKIN (see the timing
diagram shown in Figure 21). When this signal goes
high, the DSP56ADC16 will begin transmitting bits via
the serial data out (SDO) pin. Frame sync input is an
optional input signal. If the FSI pin is grounded, frame
sync’s will be internally generated. The purpose of
FSI is to allow external control of the A/D conversion
process phasing. FSI should be a periodic signal oc-
curring every 16 SCO clock periods in the comb filter
output mode and every 32 SCO clock periods in the
FIR filter output mode. In all cases FSI must be syn-
chronized to CLKIN as defined in the timing specifica-
tion. FSI allows multiple DSP56ADC16’s to be
synchronized using a common frame sync source. A
V
in+
- V
in -
V
refin
Reference Output (REFOUT)
This pin is the on-board reference voltage output
(V
refout
) of +2.0 volts when using a +5.0 volt supply.
This pin should be connected to REFIN when an
external voltage reference is not used. When
REFOUT is loaded by REFIN as shown in Figures 15
and 16, the value V
refout
is
V
refout
=
2*AV
CC
5
Serial Clock Output (SCO)
This pin provides the serial bit clock for the SDO port.
When the FIR filter output is selected by setting
FSEL= 0, the rate of this output is CLKIN divided by
DSP56ADC16
MOTOROLA
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four; when the comb filter output is selected by setting
FSEL = 1, the rate of this output is CLKIN divided by
two. See Figures 22 and 24 for more details.
Filter Select (FSEL)
This input allows selection of the FIR filter output or
the comb filter output. When FSEL is low, the SDO pin
will deliver the final lowpass/compensation FIR filter
output. When FSEL is high, the SDO will deliver the
comb filter output at a four times faster output sample
rate with a two times faster clock rate than the FIR fil-
ter output and the SFMT pin is disabled such that
SFMT=0 as shown in Figure 24. (also see SCO in this
section and Figure 22).
Serial Data Output (SDO)
A 16-bit serial data stream is output on the SDO pin
once per frame sync output cycle. This data changes
synchronously with the serial clock out (SCO) pin.
The format used is fractional 2’s complement trans-
mitted most-significant-bit first. See Figures 22 and
24 for timing details.
Serial Format (SFMT)
This pin selects the formats of the FSO and SCO
when the FIR filter output is selected by setting
FSEL=0. The two formats of operation are shown in
Figure 22.
Data Output Enable (DOE)
Serial data output three-state control pin. When DOE
bar is asserted (low), the SDO will be active. When
DOE bar is deasserted (high), the SDO will go to a
high impedance state. This can be used for multiplex-
ing several A/D converters into one host serial input.
This pin is an asynchronous input and operates inde-
pendently of input or output clocks (see Figure 25).
Frame Sync Output (FSO)
This output is used to indicate the beginning of serial
word transmission on the SDO pin. The shape and
timing of the frame sync output pulse are controlled by
the SFMT pin. Refer to Figures 22 and 24 for timing
details of FSO.
INPUT/OUTPUT CLOCKS AND CONTROL
The DSP56ADC16 output sample rate is defined by a
combination of the CLKIN frequency and the output
filter selected as determined by the FSEL pin. When
FSEL=0 the FIR filter is selected and the output sam-
ple rate is equal to CLKIN divided by 128. When
FSEL=1 the comb section is selected, the decimation
ratio is changed to 16:1 and the output sample rate is
equal to CLKIN divided by 32. The input sample rate
is always the CLKIN frequency divided by two. In nor-
mal mode (FSEL=0), the clock rate of the SCO is de-
fined as the CLKIN frequency divided by four, giving
a maximum serial clock output of 3.2 MHz as shown
in Figure 22. However, when the comb filter output is
selected (FSEL=1), the rate is changed to the CLKIN
frequency divided by two which makes the maximum
rate of 6.4 MHz as shown in Figure 24. The timing re-
lationships among CLKIN, FSI and SCO are detailed
in the “
AC Electrical Specifications”
section Fig-
ures 21 through 23 for when the filter selection (FSEL)
pin is set to 0 selecting the FIR filter output (see FSEL
in the “
Signal Description
” section).
Analog Vcc Supply (AVCC)
This pin is the positive analog power supply (
+
5 volts
±
10%) for the analog integrator section.
NOTE
Analog Vcc and digital Vcc should be decou-
pled with respect to AGND and DGND, respec-
tively, to obtain the published specifications.
This decoupling is intended to isolate digital
noise from the analog section. Decoupling ca-
pacitors should be as close as possible to their
respective analog and digital supply pins.
Digital Vcc supply (DVCC)
This pin is the positive digital power supply (
+
5 volts
±
10%) for digital internal circuitry and pin drivers (see
AVCC).
Analog Ground (AGND)
This pin is the analog ground return for the analog
front end. This pin is NOT internally connected to dig-
ital ground (DGND).
SERIAL INTERFACE
The DSP56ADC16 has three output pins for the serial
interface: 1) serial data out (SDO), 2) frame sync out
(FSO), and 3) serial clock out (SCO). The corre-
sponding internal block diagram is shown in Figure 3.
The serial port can interface with general purpose dig-
ital signal processors such as the DSP5600x,
Digital Ground (DGND)
This pin is the ground connection for digital internal
circuitry and pin drivers.
MOTOROLA
4
DSP56ADC16
DSP561xx, NEC772x, TMS320Cxx and DSP16x
without additional interface circuitry. The format of the
fractional data output from the A/D converter is MSB
first, 16-bit serial and two’s complement. The serial
data format for interfaces is defined as:
15
0
1
sin
(
16πfT
)
H
(
f
)
=
----- ----------------------------
-
-
16
sin
( πfT )
4
where
1
T
=
---
-
f
s
and f
s
is the input sampling rate for the AFE (maxi-
mum 6.4 MHz).
sign bit (MSB) transmitted first
LSB
The Serial Format (SFMT) pin selects between a one
clock wide high-true frame sync pulse and a one data
word wide low-true frame sync pulse as shown in Fig-
ure 22.
FIRST AND SECOND STAGE
DECIMATION
The first stage comb filter provides initial filtering of
the quantized output from the analog front end as well
as decimation of the input sample rate by a factor of
16:1. The z-domain transfer function of this stage can
be expressed as:
[
1 –
z
]
H
(
z
)
=
--------------------------
-
–1 4
[
1 –
z
]
The frequency domain (in Hz) equivalent of the trans-
fer function is
– 16 4
Figure 4 shows the magnitude response of the comb
filter section. Since the comb filter has a non-flat low-
pass like frequency response in the passband region,
the following second stage FIR filter should compen-
sate for the passband droop as well as providing the
final sharp cutoff required for 16 bits of dynamic
range. Figures 5 and 6 illustrate the frequency re-
sponses of the lowpass FIR filter and the compensa-
tion, respectively. The 255-tap FIR filter coefficients
are designed for a lowpass filter with 9% transition
band and passband amplitude compensation whose
characteristics are — passband cutoff frequency:
45.5 KHz, stopband cutoff frequency: 50 KHz, pass-
band ripple: 0.001 dB and a stopband ripple: -96 dB
when the chip is operated at a CLKIN frequency of
12.8 MHz. The 16-bit output of the first-stage comb fil-
ter is used as the input to the second-stage FIR filter.
This filter removes the out-of-band noise components
and also acts as the system anti-aliasing filter. Since
the in-band signal has been shaped by the third-order
noise-shaping integrators, the signal-to-noise ratio
achieved is more than 90 dB. It is important to note
FILTER SELECT
FROM FIR FILTER
OUTPUT (16 BITS)
FROM COMB FILTER
OUTPUT (16 BITS)
INPUT
MULTIPLEXER
16
THREE-STATE DRIVER
SERIAL
CLOCK OUT
16-BIT SHIFT REGISTER
SERIAL
DATA OUT
FRAME
SYNC OUT
FRAME SYNC INPUT
FILTER SELECT
DATA OUTPUT ENABLE
Figure 3. Block Diagram of Serial Interface
DSP56ADC16
MOTOROLA
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