Freescale Semiconductor
Data Sheet: Technical Data
Document Number: DSP56720EC
Rev. 5, 02/2009
DSP56720/DSP56721
Symphony
™
DSP56720/DSP56721
Multi-Core Audio Processors
The Symphony DSP56720/DSP56721 Multi-Core Audio
Processors are part of the DSP5672x family of programmable
CMOS DSPs, designed using multiple DSP56300 24-bit
cores.
The DSP56720/DSP56721 devices are intended for
automotive, consumer, and professional audio applications
that require high performance for audio processing. In
addition, the DSP56720 is ideally suited for applications that
need the capability to expand memory off-chip or to interface
to external parallel peripherals. Potential applications include
A/V receivers, HD-DVD and Blu-Ray players, car
audio/amplifiers, and professional recording equipment.
The DSP56720/DSP56721 devices excel at audio processing
for automotive and consumer audio applications requiring
high MIPs. Higher MIPs and memory requirements are driven
by the new high-definition audio standards (Dolby Digital+,
Dolby TrueHD, DTS-HD, for example) and the desire to
process multiple audio streams.
In addition, DSP56720/DSP56721 devices are optimal for the
professional audio market requiring audio recording, signal
processing, and digital audio synthesis.
The DSP56720/DSP56721 processors provide a wealth of
on-chip audio processing functions, via a plug and play
software architecture system that supports audio decoding
algorithms, various equalization algorithms, compression,
signal generator, tone control, fade/balance, level
meter/spectrum analyzer, among others. The
DSP56720/DSP56721 devices also support various matrix
decoders and sound field processing algorithms.
With two DSP56300 cores, a single DSP56720 or DSP56721
device can replace dual-DSP designs, saving costs while
meeting high MIPs requirements. Legacy peripherals from the
previous DSP5636x/7x families are included, as well as a
variety of new modules. Included among the new modules are
an Asynchronous Sample Rate Converter (ASRC), Inter-Core
DSP56720
144-Pin LQFP
20 mm
×
20 mm
0.5 mm pitch
DSP56721
80-Pin LQFP
14 mm
×
14 mm
0.65 mm pitch
144-Pin LQFP
20 mm
×
20 mm
0.5 mm pitch
Communication (ICC), an External Memory Controller
(EMC) to support SDRAM, and a Sony/Philips Digital
Interface (S/PDIF).
The DSP56720/DSP56721 offer 200 million instructions per
second (MIPs) per core using an internal 200 MHz clock.
The DSP56720/DSP56721 are high density CMOS devices
with 3.3 V inputs and outputs.
The DSP56720 device is slightly different than the DSP56721
device—the DSP56720 includes an external memory
interface while the DSP56721 device does not. The
DSP56720 block diagram is shown in
Figure 1;
the
DSP56721 block diagram is shown in
Figure 2.
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Table of Contents
1
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Pinout for DSP56720 144-Pin Plastic LQFP Package . .5
1.2 Pinout for DSP56721 80-Pin Plastic LQFP Package . . .6
1.3 Pinout for DSP56721 144-Pin Plastic LQFP Package . .7
1.4 Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .8
2.2
Thermal Characteristics. . . . . . . . . . . . . . . . . . . .9
2.3
Power Requirements . . . . . . . . . . . . . . . . . . . . .10
2.5
DC Electrical Characteristics . . . . . . . . . . . . . . .12
2.6
AC Electrical Characteristics . . . . . . . . . . . . . . .13
2.7
Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.8
External Clock Operation. . . . . . . . . . . . . . . . . .13
2.9
Reset, Stop, Mode Select, and Interrupt Timing 15
2.10 Serial Host Interface (SHI) SPI Protocol Timing 18
2.11 Serial Host Interface (SHI) I
2
C Protocol Timing.24
2.12 Programming the SHI I
2
C Serial Clock . . . . . . 26
2.13 Enhanced Serial Audio Interface (ESAI) Timing 27
2.14 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.15 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.16 JTAG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.17 Watchdog Timer Timing . . . . . . . . . . . . . . . . . . 35
2.18 Host Data Interface (HDI24) Timing . . . . . . . . . 35
2.19 S/PDIF Timing . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.20 EMC Timing (DSP56720 Only) . . . . . . . . . . . . 43
Functional Description and Application Information . . . . . . . 47
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.1 80-Pin Package Outline Drawing . . . . . . . . . . . . . . . . . 49
5.2 144-Pin Package Outline Drawing. . . . . . . . . . . . . . . . 51
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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Symphony
™
DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5
2
Freescale Semiconductor
Embedded System
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