DA14683
Bluetooth Low Energy 5.0 SoC with Enhanced Security
General description
The DA14683 is a flexible System-on-Chip combining
an application processor, memories, cryptography
engine, power management unit, digital and analog
peripherals and a Bluetooth Low Energy MAC engine
and radio transceiver.
The DA14683 is based on an ARM Cortex -M0 CPU
delivering up to 84 DMIPS (at maximum 96 MHz sys-
tem speed) and provides a flexible memory architec-
ture, enabling code execution from embedded memory
(RAM, ROM) or non-volatile memory (OTP or external
Quad-SPI FLASH).
The advanced power management unit of the
DA14683 enables it to run from primary and secondary
batteries, as well as provide power to external devices.
The on-chip charger and state-of-charge fuel gauge
allows the DA14683 to natively charge rechargeable
batteries over USB.
The DA14683 comes with enhanced security features
such as key manipulation, secure booting (i.e. starting
the system only if the FLASH image is authenticated),
a complete public/private hardware acceleration
engine and a hardware true random number generator
(TRNG).
Several optimised sleep modes are available to reduce
power dissipation when there is no activity.
®
®
FINAL
Features
Complies to
Bluetooth v5.0,
ETSI EN 300 328 and
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
(US) and ARIB STD-T66 (Japan)
Flexible processing power
0 Hz up to 96 MHz 32-bit ARM Cortex-M0 with
4-way associative cache
Three optimised power modes (Extended sleep,
Deep sleep and Hibernation) reducing current to
800 nA
Memories
64 kB One-Time-Programmable (OTP) memory
128 kB Data SRAM with retention capabilities
16 kB Cache SRAM with retention capabilities
128 kB ROM (including boot ROM and BLE stack)
Power management
Integrated Buck DC-DC converter (1.7 V - 4.75 V)
________________________________________________________________________________________________
Three power supply pins for external devices
Supports Li-Polymer, Li-Ion, coin, NiMH and alka-
line batteries
Charger (up to 5.0 V) with programmable curves
High accuracy state-of-charge fuel gauge
Programmable threshold for brownout detection
Digitally controlled oscillators and PLL
16/32 MHz crystal oscillator
16 MHz RC oscillator
32 kHz crystal and RC oscillator
11.4 kHz RCX oscillator
Low power PLL up to 96 MHz
Three general purpose timer/counters with PWM
One 16-bit up/down timer/counter with PWM
available in extended/deep sleep mode
Application cryptographic engine with ECC, AES-
256, SHA-1, SHA-256, SHA-512 and True Random
Number Generator
Digital interfaces
37 (AQFN) or 21 (WLCSP) general purpose I/Os
with programmable voltage levels
Quad-SPI FLASH interface
Two UARTs, one with hardware flow control
Two SPI+™ interfaces
Two I2C bus interfaces at 100 kHz, 400 kHz
Three-axes capable Quadrature Decoder
PDM + HW decimator (2 mics or 2 speakers)
I2S/PCM master/slave interface up to 8 channels
Keyboard scanner with debouncing
Infrared (IR) interface (PWM)
USB 1.1 Full Speed (FS) device interface
Analog interfaces
8-channel 10-bit ADC with averaging capability
Three matched white LED drivers
Temperature sensor
Radio transceiver
2.4 GHz CMOS transceiver with integrated balun
50
matched single wire antenna interface
0 dBm transmit output power
-94 dBm receiver sensitivity (BLE)
Supply current at VBAT1 (3 V):
TX: 3.4 mA
RX: 3.1 mA (with ideal DC-DC converter)
Packages:
AQFN with 60 pins, 6 mm x 6 mm
WLCSP with 53 balls, 3.406 mm x 3.010 mm
System diagram
Datasheet
CFR0011-120-00-FM Rev 5
Revision 3.1
1 of 459
28-Sep-2018
© 2018 Dialog Semiconductor
DA14683
Bluetooth Low Energy 5.0 SoC with Enhanced Security
Content
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Package and pinout . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 INTERNAL BLOCKS . . . . . . . . . . . . . . . . . . . . 19
3.2 FUNCTIONAL MODES . . . . . . . . . . . . . . . . . . 20
3.3 SYSTEM CONFIGURATION . . . . . . . . . . . . . 20
3.4 SYSTEM STARTUP PROCEDURE . . . . . . . . 24
3.4.1 Power/Wakeup FSM . . . . . . . . . . . . . . . 24
3.4.2 Goto Sleep FSM . . . . . . . . . . . . . . . . . . 25
3.4.3 BootROM sequence . . . . . . . . . . . . . . . 25
3.5 POWER CONTROL AND MODES . . . . . . . . . 28
3.5.1 System Power Control . . . . . . . . . . . . . . 28
3.5.2 Power domains . . . . . . . . . . . . . . . . . . . 28
3.5.3 Power modes . . . . . . . . . . . . . . . . . . . . . 29
3.6 SECURITY . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.6.1 Secure Keys Manipulation . . . . . . . . . . . 32
3.6.2 Secure Boot . . . . . . . . . . . . . . . . . . . . . . 34
3.6.3 Access . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6.4 Attestation . . . . . . . . . . . . . . . . . . . . . . . 35
3.6.5 Cryptography . . . . . . . . . . . . . . . . . . . . . 35
4 Power management . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . 36
4.1.1 SIMO DC-DC converter . . . . . . . . . . . . . 37
4.1.2 LDOs . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1.3 Switching from DC-DC to LDOs . . . . . . 43
4.1.4 PMU configurations in Sleep modes . . . 43
4.1.5 Wake/Power up - Sleep Timing . . . . . . . 44
4.1.6 Charger . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1.7 Fuel Gauge . . . . . . . . . . . . . . . . . . . . . . 48
4.1.8 USB charger detection. . . . . . . . . . . . . . 50
5 Reset and BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1 POR, HW AND SW RESET . . . . . . . . . . . . . . 53
5.2 RAILS DISCHARGING . . . . . . . . . . . . . . . . . . 54
5.3 BROWN OUT DETECTION . . . . . . . . . . . . . . 55
5.4 VOLTAGE BOUNCING . . . . . . . . . . . . . . . . . . 56
6 Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.1 CLOCK TREE . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.2 CRYSTAL OSCILLATORS . . . . . . . . . . . . . . . 59
6.2.1 Frequency control (16 MHz crystal) . . . . 59
6.2.2 Automated trimming and settling notification
59
6.3 RC OSCILLATORS . . . . . . . . . . . . . . . . . . . . . 61
6.3.1 Frequency calibration . . . . . . . . . . . . . . 61
13 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
13.1 DMA PERIPHERALS . . . . . . . . . . . . . . . . . . 83
13.2 INPUT/OUTPUT MULTIPLEXER . . . . . . . . . 83
13.3 DMA CHANNEL OPERATION . . . . . . . . . . . 83
FINAL
6.4 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7 ARM Cortex M0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.1 SYSTEM TIMER (SYSTICK). . . . . . . . . . . . . . 63
7.2 WAKEUP INTERRUPT CONTROLLER . . . . . 63
7.3 REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . 63
8 Cache Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.1 CACHABLE RANGE . . . . . . . . . . . . . . . . . . . . 66
8.2 RUNTIME RECONFIGURATION . . . . . . . . . . 67
8.2.1 Cache Line reconfiguration . . . . . . . . . . 67
8.2.2 TAG memory word . . . . . . . . . . . . . . . . . 67
8.2.3 Associativity reconfiguration . . . . . . . . . 67
8.3 2 AND 4 WAY REPLACEMENT STRATEGY . 67
8.4 CACHE RESETS. . . . . . . . . . . . . . . . . . . . . . . 67
8.5 CACHE MISS RATE MONITOR . . . . . . . . . . . 68
8.6 CACHE MISS LATENCY AND POWER . . . . . 68
9 AMBA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . 72
11 OTP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.1 OPERATING MODES . . . . . . . . . . . . . . . . . . 74
11.2 AHB MASTER INTERFACE . . . . . . . . . . . . . 75
11.3 AHB SLAVE INTERFACES . . . . . . . . . . . . . . 75
11.4 ERROR CORRECTING CODE (ECC) . . . . . 75
11.5 BUILD-IN SELF REPAIR (BISR) . . . . . . . . . . 75
12 Quad SPI Controller . . . . . . . . . . . . . . . . . . . . . . . 76
12.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 76
12.1.1 Interface . . . . . . . . . . . . . . . . . . . . . . . . 76
12.1.2 Initialization FSM . . . . . . . . . . . . . . . . . 77
12.1.3 SPI modes . . . . . . . . . . . . . . . . . . . . . . 78
12.1.4 Access modes . . . . . . . . . . . . . . . . . . . 78
12.1.5 Endianess . . . . . . . . . . . . . . . . . . . . . . 78
12.1.6 Erase Suspend/Resume . . . . . . . . . . . 78
12.1.7 QSPI FLASH Programming . . . . . . . . . 79
12.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 79
12.2.1 Auto Mode . . . . . . . . . . . . . . . . . . . . . . 79
12.2.2 Manual Mode . . . . . . . . . . . . . . . . . . . . 80
12.2.3 Clock selection. . . . . . . . . . . . . . . . . . . 80
12.2.4 Received data . . . . . . . . . . . . . . . . . . . 80
12.3 TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Datasheet
CFR0011-120-00-FM Rev 5
Revision 3.1
2 of 465
28-Sep-2018
© 2018 Dialog Semiconductor
DA14683
Bluetooth Low Energy 5.0 SoC with Enhanced Security
13.4 DMA ARBITRATION . . . . . . . . . . . . . . . . . . . 84
13.5 FREEZING DMA CHANNELS. . . . . . . . . . . . 84
13.6 SECURE DMA CHANNEL . . . . . . . . . . . . . . 84
14 AES/Hash Engine . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 85
14.1.1 AES/HASH engine . . . . . . . . . . . . . . . . 85
14.1.2 AES . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.1.3 Modes . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.1.4 HASH . . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 87
15 ECC Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
15.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 90
15.1.1 Supported curves. . . . . . . . . . . . . . . . . 91
15.1.2 Supported high level algorithms . . . . . 91
15.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 91
15.2.1 Example: ECDSA signature generation 91
16 True Random Number Generator (TRNG). . . . . . 94
16.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 94
16.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 94
16.2.1 Latency . . . . . . . . . . . . . . . . . . . . . . . . 94
17 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . 95
17.1 PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 95
18 Wakeup Controller . . . . . . . . . . . . . . . . . . . . . . . . 96
18.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 96
18.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 96
19 General purpose ADC . . . . . . . . . . . . . . . . . . . . . . 98
19.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 98
19.2 INPUT CHANNELS AND INPUT SCALE . . 100
19.3 STARTING THE ADC . . . . . . . . . . . . . . . . . 100
19.4 ADC CONVERSION MODES . . . . . . . . . . . 100
19.4.1 Manual Mode . . . . . . . . . . . . . . . . . . . 100
19.4.2 Continuous Mode. . . . . . . . . . . . . . . . 100
19.5 NON-IDEAL EFFECTS . . . . . . . . . . . . . . . . 100
19.6 SAMPLING TIME (SMPL_TIME). . . . . . . . . 101
19.7 OVERSAMPLING . . . . . . . . . . . . . . . . . . . . 101
19.8 CHOPPING . . . . . . . . . . . . . . . . . . . . . . . . . 102
19.9 OFFSET CALIBRATION . . . . . . . . . . . . . . . 102
19.10 ZERO-SCALE ADJUSTMENT . . . . . . . . . 102
19.11 COMMON MODE ADJUSTMENT . . . . . . . 102
19.12 INPUT IMPEDANCE, INDUCTANCE, AND IN-
PUT SETTLING. . . . . . . . . . . . . . . . . . . . . . . 103
20 Sample rate Converter (SRC) . . . . . . . . . . . . . . . 104
20.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 104
23 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
23.1 UART (RS232) SERIAL PROTOCOL . . . . . .112
23.2 IRDA 1.0 SIR PROTOCOL . . . . . . . . . . . . . .113
23.3 CLOCK SUPPORT . . . . . . . . . . . . . . . . . . . .114
23.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . .115
23.5 PROGRAMMABLE THRE INTERRUPT . . . .115
23.6 SHADOW REGISTERS . . . . . . . . . . . . . . . .117
23.7 DIRECT TEST MODE . . . . . . . . . . . . . . . . . .117
24 SPI+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
24.1 OPERATION WITHOUT FIFOS . . . . . . . . . .118
24.2 9 BITS MODE . . . . . . . . . . . . . . . . . . . . . . . .119
24.3 TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
25 I2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
25.1 I2C BUS TERMS . . . . . . . . . . . . . . . . . . . . . 123
25.1.1 Bus Transfer Terms . . . . . . . . . . . . . . 124
25.2 I2C BEHAVIOUR. . . . . . . . . . . . . . . . . . . . . 124
25.2.1 START and STOP Generation . . . . . . 125
25.2.2 Combined Formats . . . . . . . . . . . . . . 125
25.3 I2C PROTOCOLS . . . . . . . . . . . . . . . . . . . . 125
25.3.1 START and STOP Conditions . . . . . . 125
25.3.2 Addressing Slave Protocol. . . . . . . . . 125
25.3.3 Transmitting and Receiving Protocol . 126
25.4 MULTIPLE MASTER ARBITRATION . . . . . 128
25.5 CLOCK SYNCHRONIZATION . . . . . . . . . . 129
25.6 OPERATION MODES . . . . . . . . . . . . . . . . . 129
25.6.1 Slave Mode Operation . . . . . . . . . . . . 130
FINAL
20.1.1 I/O channels. . . . . . . . . . . . . . . . . . . . 104
20.1.2 I/O multiplexers . . . . . . . . . . . . . . . . . 104
20.1.3 Input and Output Sample rate conversion
104
20.1.4 SRC conversion modes of operation . 104
20.1.5 DMA operation . . . . . . . . . . . . . . . . . . 105
20.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . 105
20.1.7 SRC use cases . . . . . . . . . . . . . . . . . 105
21 PDM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
22 PCM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 107
22.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 107
22.1.1 Interface Signals . . . . . . . . . . . . . . . . 107
22.1.2 Channel ACCESS . . . . . . . . . . . . . . . 107
22.1.3 Channel delay . . . . . . . . . . . . . . . . . . 108
22.1.4 Clock generation . . . . . . . . . . . . . . . . 108
22.1.5 DATA FORMATS . . . . . . . . . . . . . . . . 109
22.1.6 IOM mode . . . . . . . . . . . . . . . . . . . . . .110
22.1.7 External synchronisation . . . . . . . . . . .110
Datasheet
CFR0011-120-00-FM Rev 5
Revision 3.1
3 of 465
28-Sep-2018
© 2018 Dialog Semiconductor
DA14683
Bluetooth Low Energy 5.0 SoC with Enhanced Security
25.7 MASTER MODE OPERATION . . . . . . . . . . 132
26 InfraRed Generator . . . . . . . . . . . . . . . . . . . . . . . 133
26.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 133
26.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . 134
27 Quadrature Decoder . . . . . . . . . . . . . . . . . . . . . . 135
27.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 135
27.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . 135
28 Keyboard Scanner. . . . . . . . . . . . . . . . . . . . . . . . 136
28.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 136
28.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . 138
29 Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
29.1 TIMER0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
29.2 TIMER1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
29.3 TIMER2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
29.4 BREATH TIMER . . . . . . . . . . . . . . . . . . . . . 143
30 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . 145
31 USB Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
31.1 SERIAL INTERFACE ENGINE . . . . . . . . . . 146
31.2 ENDPOINT PIPE CONTROLLER (EPC) . . 147
31.3 FUNCTIONAL STATES. . . . . . . . . . . . . . . . 148
31.3.1 Line Condition Detection . . . . . . . . . . 148
31.4 FUNCTIONAL STATE DIAGRAM . . . . . . . . 149
31.5 ADDRESS DETECTION . . . . . . . . . . . . . . . 151
31.6 TRANSMIT AND RECEIVE ENDPOINT FIFOS
152
31.7 BIDIRECTIONAL CONTROL ENDPOINT FIFO0
153
31.8 TRANSMIT ENDPOINT FIFO (TXFIFO1 TO
TXFIFO5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
31.9 RECEIVE ENDPOINT FIFO (RXFIFO2 TO
RXFIFO6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
31.10 INTERRUPT HIERARCHY . . . . . . . . . . . . 156
32 Input/Output ports. . . . . . . . . . . . . . . . . . . . . . . . 158
32.1 PROGRAMMABLE PIN ASSIGNMENT . . . 158
32.2 GENERAL PURPOSE PORT REGISTERS 158
32.2.1 Port Data Register . . . . . . . . . . . . . . . 158
32.2.2 Port Set Data Output Register . . . . . . 159
32.2.3 Port Reset Data Output Register . . . . 159
32.3 FIXED ASSIGNMENT FUNCTIONALITY . . 159
32.4 STATE RETENTION WHILE SLEEPING . . 159
32.5 SPECIAL I/O CONSIDERATIONS . . . . . . . 160
FINAL
33 BLE Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
33.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 161
33.1.1 Exchange Memory . . . . . . . . . . . . . . . 161
33.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . 161
33.2.1 Wake up IRQ . . . . . . . . . . . . . . . . . . . 161
33.2.2 Switch from Active Mode to Deep Sleep
Mode . . . . . . . . . . . . . . . . . . . . . . . . . 162
33.2.3 Switch from Deep Sleep Mode to Active
Mode . . . . . . . . . . . . . . . . . . . . . . . . . 162
33.2.4 Switching on at anchor points. . . . . . . 162
33.2.5 Switching on due to an external event.164
33.3 DIAGNOSTIC SIGNALS . . . . . . . . . . . . . . . 164
33.4 POWER PROFILE . . . . . . . . . . . . . . . . . . . 166
33.4.1 Advertising Event . . . . . . . . . . . . . . . . 166
33.4.2 Connection Event . . . . . . . . . . . . . . . 167
34 CoEx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
34.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 168
34.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . 168
35 Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
35.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 170
35.1.1 Receiver. . . . . . . . . . . . . . . . . . . . . . . 170
35.1.2 Synthesizer . . . . . . . . . . . . . . . . . . . . 170
35.1.3 Transmitter. . . . . . . . . . . . . . . . . . . . . 170
35.1.4 RFIO . . . . . . . . . . . . . . . . . . . . . . . . . 171
35.1.5 Biassing . . . . . . . . . . . . . . . . . . . . . . . 171
35.1.6 Control . . . . . . . . . . . . . . . . . . . . . . . . 171
35.2 DYNAMIC CONTROLLED FUNCTIONS . . 171
35.3 DIAGNOSTIC SIGNALS . . . . . . . . . . . . . . . 171
36 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
37 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
37.1 OTPC REGISTER FILE . . . . . . . . . . . . . . . 177
37.2 QSPIC REGISTER FILE . . . . . . . . . . . . . . . 183
37.3 BLE REGISTER FILE . . . . . . . . . . . . . . . . . 193
37.4 AES_HASH REGISTER FILE . . . . . . . . . . . 214
37.5 CACHE REGISTER FILE . . . . . . . . . . . . . . 218
37.6 CRG REGISTER FILE . . . . . . . . . . . . . . . . 221
37.7 DCDC REGISTER FILE . . . . . . . . . . . . . . . 235
37.8 WAKEUP REGISTER FILE . . . . . . . . . . . . . 244
37.9 TIMER1 REGISTER FILE . . . . . . . . . . . . . . 248
37.10 UART REGISTER FILE. . . . . . . . . . . . . . . 251
37.11 SPI REGISTER FILE . . . . . . . . . . . . . . . . . 288
37.12 I2C REGISTER FILE . . . . . . . . . . . . . . . . . 292
37.13 KEYBOARD SCAN REGISTER FILE . . . . 326
37.14 IR REGISTER FILE . . . . . . . . . . . . . . . . . . 333
37.15 USB REGISTER FILE . . . . . . . . . . . . . . . . 336
Datasheet
CFR0011-120-00-FM Rev 5
Revision 3.1
4 of 465
28-Sep-2018
© 2018 Dialog Semiconductor
DA14683
Bluetooth Low Energy 5.0 SoC with Enhanced Security
37.16 GPADC REGISTER FILE . . . . . . . . . . . . . 367
37.17 QUADRATURE DECODER REGISTER FILE.
370
37.18 ANAMISC REGISTER FILE . . . . . . . . . . . 371
37.19 CRG REGISTER FILE . . . . . . . . . . . . . . . 378
37.20 RFCU REGISTER FILE . . . . . . . . . . . . . . 379
37.21 DEM REGISTER FILE . . . . . . . . . . . . . . . 380
37.22 COEX REGISTER FILE . . . . . . . . . . . . . . 380
37.23 GPIO REGISTER FILE . . . . . . . . . . . . . . . 386
37.24 WDOG REGISTER FILE . . . . . . . . . . . . . . 403
37.25 VERSION REGISTER FILE . . . . . . . . . . . 403
37.26 GPREG REGISTER FILE . . . . . . . . . . . . . 404
37.27 TIMER0/2 AND BREATH REGISTER FILE 408
37.28 DMA REGISTER FILE . . . . . . . . . . . . . . . .411
37.29 APU REGISTER FILE . . . . . . . . . . . . . . . . 432
37.30 TRNG REGISTER FILE . . . . . . . . . . . . . . 438
37.31 ELLIPTIC CURVE CONTROLLER REGISTER
FILE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
38 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
39 Package information . . . . . . . . . . . . . . . . . . . . . . 462
39.1 MOISTURE SENSITIVITY LEVEL (MSL) . . 462
39.2 WLCSP HANDLING . . . . . . . . . . . . . . . . . . 462
39.3 SOLDERING INFORMATION . . . . . . . . . . . 462
39.4 PACKAGE OUTLINES . . . . . . . . . . . . . . . . 463
FINAL
Datasheet
CFR0011-120-00-FM Rev 5
Revision 3.1
5 of 465
28-Sep-2018
© 2018 Dialog Semiconductor
ARM Technology
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