DP8051
Pipelined High Performance
8-bit Microcontroller
ver 4.05
OVERVIEW
DP8051 is an
ultra high performance,
speed optimized
soft core of a single-chip 8-
bit embedded controller dedicated for opera-
tion with
fast
(typically on-chip) and
slow
(off-
chip)
memories.
The core has been designed
with a special concern about
performance to
power consumption
ratio. This ratio is ex-
tended by an advanced power management
unit
PMU.
DP8051 soft core is 100% binary-
compatible with the industry standard 8051 8-
bit microcontroller. There are two configura-
tions of DP8051:
Harward
where internal data
and program buses are separated, and
von
Neumann
with common program and external
data bus. DP8051 has Pipelined RISC archi-
tecture
10 times faster
compared to standard
architecture and executes
85-200 million in-
structions
per second. This performance can
also be exploited to great advantage in
low
power
applications where the core can be
clocked over ten times more slowly than the
original implementation for no performance
penalty.
DP8051 is delivered with
fully automated
testbench
and
complete set of tests
allowing
easy package validation at each stage of SoC
design flow.
●
●
CPU FEATURES
100% software compatible with industry
standard 8051
Pipelined RISC architecture enables to
execute instructions 10 times faster com-
pared to standard 8051
24 times faster multiplication
12 times faster addition
Up to 256 bytes of internal (on-chip) Data
Memory
Up to 64K bytes of internal (on-chip) or
external (off-chip) Program Memory
Up to 16M bytes of external (off-chip) Data
Memory
User programmable Program Memory Wait
States solution for wide range of memories
speed
User programmable External Data Memory
Wait States solution for wide range of
memories speed
De-multiplexed Address/Data bus to allow
easy connection to memory
Dedicated signal for Program Memory
writes.
Interface for additional Special Function
Registers
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All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2006 DCD – Digital Core Design. All Rights Reserved.
●
Fully synthesizable, static synchronous
design with positive edge clocking and no
internal tri-states
Scan test ready
2.0 GHz virtual
clock frequency in a 0.25u
technological process
●
●
○
○
○
○
Synchronous mode, fixed baud rate
8-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, variable baud rate
CONFIGURATION
The following parameters of the DP8051 core
can be easy adjusted to requirements of dedi-
cated application and technology. Configura-
tion of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
•
•
•
•
Internal Program Memory
type
Internal Program ROM
Memory size
Internal Program RAM
Memory size
Internal Program Memory
fixed size
- synchronous
- asynchronous
-
0 - 64kB
-
-
0 - 64kB
-
- true
- false
-
subroutines
location
PERIPHERALS
●
DoCD™ debug unit
○
Processor execution control
Run
Halt
Step into instruction
Skip instruction
○
Read-write all processor contents
Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○
Code execution breakpoints
one real-time PC breakpoint
unlimited number of real-time OPCODE break-
points
○
Hardware execution watch-point
one at Internal (direct) Data Memory
one at Special Function Registers (SFRs)
one at External Data Memory
○
Hardware watch-points activated at a certain
address by any write into memory
address by any read from memory
address by write into memory a required data
address by read from memory a required data
○
Unlimited number of software watch-points
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○
Unlimited number of software breakpoints
Program Memory(PC)
○
Automatic adjustment of debug data transfer
•
Interrupts
•
Power Management Mode
•
Stop mode
•
DoCD™ debug unit
- used
- unused
- used
- unused
- used
- unused
speed rate between HAD and Silicon
○
JTAG Communication interface
Besides mentioned above parameters all
available peripherals and external interrupts
can be excluded from the core by changing
appropriate constants in package file.
●
Power Management Unit
○
Power management mode
○
Switchback feature
○
Stop mode
●
Interrupt Controller
○
2 priority levels
○
2 external interrupt sources
○
3 interrupt sources from peripherals
●
Four 8-bit I/O Ports
○
Bit addressable data direction for each line
○
Read/write of single line and 8-bit group
●
Two 16-bit timer/counters
○
Timers clocked by internal source
○
Auto reload 8-bit timers
○
Externally gated event counters
●
Full-duplex serial port
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http://www.dcd.pl
All trademarks mentioned in this document
are trademarks of their respective owners.
Copyright 1999-2006 DCD – Digital Core Design. All Rights Reserved.
DELIVERABLES
♦
Source code:
◊
VHDL Source Code or/and
◊
VERILOG Source Code or/and
◊
Encrypted, or plain text EDIF netlist
♦
VHDL & VERILOG test bench environment
◊
NCSim automatic simulation macros
◊
ModelSim automatic simulation macros
◊
Active-HDL automatic simulation macros
◊
Tests with reference responses
♦
Technical documentation
◊
Installation notes
◊
HDL core specification
◊
Datasheet
♦
Synthesis scripts
♦
Example application
♦
Technical support
◊
IP Core implementation support
◊
3 months maintenance
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DESIGN FEATURES
♦
PROGRAM MEMORY:
The DP8051 soft core is dedicated for
operation with Internal and External Pro-
gram Memory. Internal Program Memory
can be implemented as:
○
ROM located in address range between
External Program Memory can be im-
plemented as ROM or RAM located in ad-
dress range between ROM
size
÷
RAM
size
.
♦
INTERNAL DATA MEMORY:
The DP8051 can address Internal Data
Memory of up to 256 bytes The Internal
Data Memory can be implemented as Sin-
gle-Port synchronous RAM.
EXTERNAL DATA MEMORY:
The DP8051 soft core can address up to
16 MB of External Data Memory. Extra
DPX (Data
Pointer eXtended)
register is
used for segments swapping.
USER
S
PECIAL
F
UNCTION
R
EGISTERS:
Up to 104 External (user) Special Func-
tion Registers (ESFRs) may be added to
the DP8051 design. ESFRs are memory
mapped into Direct Memory between ad-
dresses 0x80 and 0xFF in the same man-
ner as core SFRs and may occupy any ad-
dress that is not occupied by a core SFR.
WAIT STATES SUPPORT:
The DP8051 soft core is dedicated for
operation with wide range of Program and
Data memories. Slow Program and Exter-
nal Data memory may assert a memory
WAIT signal to hold up CPU activity for re-
quired period of time.
0x0000
÷
(ROM
size
-1)
○
RAM located in address range between
(RAM
size
-1)
÷
0xFFFF
Delivery the IP Core updates, minor and
major versions changes
Delivery the documentation updates
Phone & email support
♦
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design
license allows using IP Core in
single FPGA bitstream and ASIC implementa-
tion. It also permits FPGA prototyping before
ASIC production.
Unlimited Designs
license allows using IP Core
in unlimited number of FPGA bitstreams and
ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
●
Single Design license for
○
VHDL, Verilog source code called HDL Sour-
♦
♦
ce
○
Encrypted, or plain text EDIF called Netlist
●
Unlimited Designs license for
○
HDL Source
○
Netlist
●
Upgrade from
○
Netlist to HDL Source
○
Single Design to Unlimited Designs
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2006 DCD – Digital Core Design. All Rights Reserved.
SYMBOL
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
prgromdata(7:0)
prgramdata(7:0)
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
xaddr(23:0)
xdatao(7:0)
xdataz
xprgrd
xprgwr
xdatard
xdatawr
ramaddr(7:0)
ramdatao(7:0)
ramwe
ramoe
BLOCK DIAGRAM
Opcode
decoder
prgramdata(7:0)
prgromdata(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
xaddr(23:0)
xdatao(7:0)
xdatai(7:0)
xdataz
ready
xprgrd
xprgwr
xdatard
xdatawr
I/O Port
registers
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
t0
t1
gate0
gate1
rxdi
rxdo
txd
Program
memory
interface
Timers
UART
External
memory
interface
xdatai(7:0)
ready
iprgromsize(2:0)
iprgramsize(2:0)
Interrupt
controller
int0
int1
iprgromsize(2:0)
iprgramsize(2:0)
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramoe
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
sfrwe
clk
reset
rsto
Control
Unit
Power
Manage-
ment Unit
stop
pmm
tdi
tck
tms
tdo
rtck
coderun
debugacs
ramdatai(7:0)
Internal data
memory
interface
DoCD™
Debug Unit
User SFR’s
interface
ALU
sfrdatai(7:0)
int0
int1
t0
t1
gate0
gate1
rxdi
tdi
tck
tms
reset
clk
sfraddr(6:0)
sfrdatao(7:0)
sfroe
sfrwe
PINS DESCRIPTION
stop
pmm
PIN
clk
reset
port0i[7:0]
port1i[7:0]
port2i[7:0]
port3i[7:0]
iprgramsize[2:0]
iprgromsize[2:0]
prgramdata[7:0]
prgromdata[7:0]
xdatai[7:0]
ready
ramdatai[7:0]
sfrdatai[7:0]
int0
int1
t0
t1
gate0
gate1
TYPE
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
DESCRIPTION
Global clock
Global reset input
Port 0 input
Port 1 input
Port 2 input
Port 3 input
Size of on-chip RAM CODE
Size of on-chip ROM CODE
Data bus from int. RAM prog. memory
Data bus from int. ROM prog. memory
Data bus from external memories
External memory data ready
Data bus from internal data memory
Data bus from user SFR’s
External interrupt 0
External interrupt 1
Timer 0 input
Timer 1 input
Timer 0 gate input
Timer 1 gate input
rxdo
txd
tdo
rtck
coderun
debugacs
rsto
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2006 DCD – Digital Core Design. All Rights Reserved.
PIN
rxdi
tdi
tck
tms
rsto
port0o[7:0]
port1o[7:0]
port2o[7:0]
port3o[7:0]
prgaddr[15:0]
prgdatao[7:0]
prgramwr
xaddr[23:0]
xdatao[7:0]
xdataz
xprgrd
xprgwr
xramrd
xramwr
ramaddr[7:0]
ramdatao[7:0]
ramoe
ramwe
sfraddr[6:0]
sfrdatao[7:0]
sfroe
sfrwe
tdo
rtck
debugacs
coderun
pmm
stop
rxdo
txd
TYPE
input
input
input
input
DESCRIPTION
Serial receiver input
DoCD™ TAP data input
DoCD™ TAP clock input
DoCD™ TAP mode select input
rectly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
Program Memory Interface
– Contains Pro-
gram Counter (PC) and related logic. It per-
forms the instructions code fetching. Program
Memory can be also written. This feature al-
lows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD™ module.
External Memory Interface
- Contains mem-
ory access related registers such as Data
Page High (DPH), Data Page Low (DPL) and
Data Pointer eXtended (DPX) registers. It per-
forms the external Program and Data Memory
addressing and data transfers. Program fetch
cycle length can be programmed by user. This
feature is called Program Memory Wait States,
and allows core to work with different speed
program memories.
Internal Data Memory Interface
– Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface
– Special Function Reg-
isters interface controls access to the special
registers. It contains standard and used de-
fined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct ad-
dressing mode instructions.
Interrupt Controller
– Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers.
Timers
– System timers module. Contains two
16 bits configurable timers: Timer 0 (TH0,
TL0), Timer 1 (TH1, TL1) and Timers Mode
(TMOD) registers. In the timer mode, timer
registers are incremented every 12 CLK peri-
ods when appropriate timer is enabled. In the
counter mode the timer registers are incre-
mented every falling transition on their corre-
sponding input pins (T0, T1), if gates are
opened (GATE0, GATE1). T0, T1 input pins
are sampled every CLK period. It can be used
as clock source for UARTs.
UART0
– Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it
can transmit and receive concurrently. Includes
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output Reset output
output Port 0 output
output Port 1 output
output Port 2 output
output Port 3 output
output Internal program memory address bus
output Data bus for internal program memory
output Internal program memory write
output Address bus for external memories
output Data bus for external memories
output Turn xdata bus into ‘Z’ state
output External program memory read
output External program memory write
output External data memory read
output External data memory write
output Internal Data Memory address bus
output Data bus for internal data memory
output Internal data memory output enable
output Internal data memory write enable
output Address bus for user SFR’s
output Data bus for user SFR’s
output User SFR’s read enable
output User SFR’s write enable
output DoCD™ TAP data output
output DoCD™ return clock line
output DoCD™ accessing data
output CPU is executing an instruction
output Power management mode indicator
output Stop mode indicator
output Serial receiver output
output Serial transmitter output
UNITS SUMMARY
ALU
– Arithmetic Logic Unit performs the
arithmetic and logic operations during execu-
tion of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) regis-
ters and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder
– Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit
– Performs the core synchroniza-
tion and data flow control. This module is di-
All trademarks mentioned in this document
are trademarks of their respective owners.
Copyright 1999-2006 DCD – Digital Core Design. All Rights Reserved.
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