DS1013
3-in-1 Silicon Delay Line
www.dalsemi.com
FEATURES
All-silicon time delay
3 independent buffered delays
Delay tolerance ±2ns for -10 through –60
Stable and precise over temperature and
voltage range
Leading and trailing edge accuracy
Economical
Auto-insertable, low profile
Standard 14-pin DIP, 8-pin DIP, or 16-pin
SOIC
Low-power CMOS
TTL/CMOS-compatible
Vapor phase, IR and wave solderable
Custom delays available
Quick turn prototypes
Extended temperature ranges available
PIN ASSIGNMENT
IN 1
NC
IN 2
NC
IN 3
NC
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
NC
OUT 1
NC
OUT 2
NC
IN 1
NC
NC
IN 2
NC
IN 3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
NC
NC
OUT 1
NC
OUT 2
NC
OUT 3
NC
OUT 3 GND
DS1013 14-pin DIP (300-mil)
See Mech. Drawings Section
DS1013S 16-pin SOIC
(300-mil)
See Mech. Drawings Section
8
7
6
5
V
CC
OUT 1
OUT 2
OUT 3
IN 1
IN 2
IN 3
GND
1
2
3
4
DS1013M 8-pin DIP (300-mil)
See Mech. Drawings Section
PIN DESCRIPTION
IN 1, IN 2, IN 3
OUT 1, OUT 2, OUT 3
GND
V
CC
NC
- Inputs
- Outputs
- Ground
- +5 Volts
- No Connection
DESCRIPTION
The DS1013 series of delay lines has three independent logic buffered delays in a single package. The
devices are offered in a standard 14-pin DIP which is pin-compatible with hybrid delay lines. Alternative
8-pin DIP and surface mount packages are available which save PC board area. Since the DS1013
products are an all silicon solution, better economy is achieved when compared to older methods using
hybrid techniques. The DS1013 series delay lines provide a nominal accuracy of
±2ns
for delay times
ranging from 10 ns to 60 ns, increasing to 5% for delays of 150 ns and longer. The DS1013 delay line
reproduces the input logic state at the output after a fixed delay as specified by the dash number extension
of the part number. The DS1013 is designed to reproduce both leading and trailing edges with equal
precision. Each output is capable of driving up to 10 74LS loads. Dallas Semiconductor can customize
standard products to meet special needs. For special requests and rapid delivery, call (972) 371–4348.
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111799
DS1013
LOGIC DIAGRAM
Figure 1
PART NUMBER DELAY TABLE (t
PHL
, t
PLH
)
Table 1
PART NO.
DS1013-10
DS1013-12
DS1013-15
DS1013-20
DS1013-25
DS1013-30
DS1013-35
DS1013-40
DS1013-45
DS1013-50
DS1013-60
DS1013-70*
DS1013-75*
DS1013-80*
DS1013-100*
DS1013-150**
DS1013-200**
Custom delays available
* ±3% tolerance
** ±5% tolerance
DELAY PER OUTPUT (ns)
10/10/10
12/12/12
15/15/15
20/20/20
25/25/25
30/30/30
35/35/35
40/40/40
45/45/45
50/50/50
60/60/60
70/70/70
75/75/75
80/80/80
100/100/100
150/150/150
200/200/200
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DS1013
TIMING DIAGRAM: SILICON DELAY LINE
Figure 2
TEST CIRCUIT
Figure 3
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DS1013
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
Short Circuit Output Current
-1.0V to +7.0V
0°C to 70°C
-55°C to +125°C
260°C for 10 seconds
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
High Level Input
Voltage
Low Level Input
Voltage
Input Leakage
Current
Active Current
High Level Output
Current
Low Level Output
Current
SYM
V
CC
V
IH
V
IL
I
I
I
CC
I
OH
I
OL
0.0V
≤
V
I
≤
V
CC
V
CC
=Max;
Period=Min.
V
CC
=Min.
V
OH
=4.0V
V
CC
=Min.
V
OL
=0.5V
TEST
CONDITION
MIN
4.75
2.2
-0.5
-1.0
(0°C to 70°C; V
CC
= 5.0V ± 5%)
TYP
5.00
MAX
5.25
V
CC
+ 0.5
0.8
1.0
40
70
-1.0
12.0
UNITS
V
NOTES
1
V
µA
mA
mA
mA
1
2
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Input Pulse Width
Input to Output Delay
(leading edge)
Input to Output Delay
(trailing edge)
Power-up Time
SYMBOL
t
WI
t
PLH
t
PHL
t
PU
Period
MIN
100% of t
PLH
(T
A
= 25°C; V
CC
= 5V ± 5%)
TYP
Table 1
Table 1
100
MAX
UNITS
ns
ns
ns
ms
ns
NOTES
3, 4, 5, 6
3, 4, 5, 6
3 (t
WI
)
7
CAPACITANCE
PARAMETER
Input Capacitance
SYMBOL
C
IN
MIN
TYP
5
MAX
10
(T
A
= 25°C)
UNITS
pF
NOTES
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DS1013
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. V
CC
= 5V @ 25°C. Delays accurate on both rising and falling edges within ±2 ns for -10 to -60, ±3%
for -70 to 100 and ±5% for -150 and longer delays.
4. See “Test Conditions” section.
5. The combination of temperature variations from 25°C to 0°C or 25°C to 70°C and voltage variations
from 5.0V to 4.75V or 5.0V to 5.25V may produce an additional delay shift of ±1.5 ns or ±3%,
whichever is greater.
6. All output delays tend to vary unidirectionally over temperature or voltage ranges (i.e., if OUT 1
slows down, all other outputs also slow down).
7. Period specifications may be exceeded; however, accuracy will be application-sensitive (decoupling,
layout, etc.).
TERMINOLOGY
Period:
The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t
WI
(Pulse Width):
The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t
RISE
(Input Rise Time):
The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
t
FALL
(Input Fall Time):
The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
t
PLH
(Time Delay, Rising):
The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
t
PHL
(Time Delay, Falling):
The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
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