DS1000Z-30 datasheet, PDF - EEWORLD Datasheet

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DS1000Z-30: DescriptionDelay Line, 1-Func, 5-Tap, CMOS; Categorylogic logic; File Size64KB，5 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1000Z-30 Overview

Delay Line, 1-Func, 5-Tap, CMOS

DS1000Z-30 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	SOIC
Contacts	8
Reach Compliance Code	not_compliant
Factory Lead Time	1 week
JESD-30 code	R-XDSO-G8
JESD-609 code	e0
Number of functions	1
Number of taps/steps	5
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	5 V
Maximum supply current (ICC)	75 mA
programmable delay line	NO
Prop。Delay @ Nom-Sup	30 ns
Certification status	Not Qualified
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Base Number Matches	1

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DS1000

5-Tap Silicon Delay Line

www.dalsemi.com

FEATURES

All-silicon time delay

5 taps equally spaced

Delays are stable and precise

Both leading and trailing edge accuracy

Delay tolerance

±5%

±2

ns, whichever is

greater

Low-power CMOS

TTL/CMOS-compatible

Vapor phase, IR and wave solderable

Custom delays available

Fast turn prototypes

Extended temperature range available

(DS1000-IND)

TAP 2

TAP 4

GND

PIN ASSIGNMENT

TAP 1

TAP 4

GND

TAP 3

TAP 5

TAP 1

TAP 3

TAP 5

TAP 3

TAP 2

TAP 1

DS1000M 8-Pin DIP (300-mil)

See Mech. Drawings Section

DS1000 14-Pin DIP (300-mil)

See Mech. Drawings Section

TAP 2

TAP 4

GND

DS1000Z 8-Pin SOIC (150-mil)

See Mech. Drawings Section

PIN DESCRIPTION

TAP 1-TAP 5

GND

- TAP Output Number

- +5 Volts

- Ground

- No Connection

- Input

DESCRIPTION

The DS1000 series delay lines have five equally spaced taps providing delays from 4 ns to 500 ns. These

devices are offered in a standard 14-pin DIP that is pin-compatible with hybrid delay lines. Alternatively,

8-pin DIPs and surface mount packages are available to save PC board area. Low cost and superior

reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and

industry standard DIP and SOIC packaging. In order to maintain complete pin compatibility, DIP

packages are available with hybrid lead configurations. The DS1000 series delay lines provide a nominal

accuracy of

±5%

±2

ns, whichever is greater. The DS1000 5-Tap Silicon Delay Line reproduces the

input logic state at the output after a fixed delay as specified by the extension of the part number after the

dash. The DS1000 is designed to reproduce both leading and trailing edges with equal precision. Each

tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to

meet special needs. For special requests and rapid delivery, call 972-371-4348.

1 of 5

111799

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