DP3ED32X8RY5-60C datasheet, PDF

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DP3ED32X8RY5-60C: DescriptionEDO DRAM Module, 32MX8, 60ns, CMOS; Categorystorage storage; File Size247KB，2 Pages; ManufacturerB&B Electronics Manufacturing Company

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DP3ED32X8RY5-60C Overview

EDO DRAM Module, 32MX8, 60ns, CMOS

DP3ED32X8RY5-60C Parametric

Parameter Name	Attribute value
package instruction	,
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FAST PAGE WITH EDO
Maximum access time	60 ns
Other features	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
JESD-30 code	R-XQMA-N48
memory density	268435456 bit
Memory IC Type	EDO DRAM MODULE
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	48
word count	33554432 words
character code	32000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX8
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal location	QUAD
Base Number Matches	1

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64 Meg Based, 50 - 70ns, M-Densus

30A179-00

High Density Memory Device

DESCRIPTION:

The

M-Densus

series is a family of interchangeable memory

modules. The 64 Megabit DRAM is a member of this family

which utilizes the new and innovative space saving TSOP

technology. The modules are constructed with 8 Meg x 8

DRAM’s available in 512, 256 and 128 Megabits.

The 64 Megabit based

M-Densus

modules have been designed

to fit in the same footprint as the 8 Meg x 8 DRAM TSOP

monolithic and are backward compatible with the 16 Megabit

based family of

M-Densus

modules. This allows the memory

board designer to upgrade the memory in their products

without redesigning the memory board, thus saving time and

money.

FEATURES:

•

Configurations Available:

512 Megabit: 64 Meg x 8

256 Megabit: 32 Meg x 8

128 Megabit: 16 Meg x 8

•

Access Times: 50, 60, 70ns (max.)

•

5.0V or 3.3V Supply

•

Common Data Inputs and Outputs

•

EDO or Fast Page Mode Capability

•

4096 Cycles / 64 ms

•

3 Variations of Refresh:

- RAS only Refresh

- CAS before RAS Refresh

- Hidden Refresh

•

Package: Leadless TSOP Module

M-Densus

512 Megabit CMOS DRAM

256 Megabit CMOS DRAM

128 Megabit CMOS DRAM

PIN-OUT DIAGRAM

* NOTE:

A12 on 8K refresh version, N.C. on 4K version.

FUNCTIONAL BLOCK DIAGRAM

PIN NAMES

A0 - A11

DQ0 - DQ7

CAS0 - CAS7

RAS0 - RAS7

N.C.

Row Address:

A0 - A11

Column Address: A0 - A11

Refresh Address: A0 - A11

Data In / Data Out

Column Address Strobes

Row Address Enables

Data Write Enable

Data Output Enable

Power Supply (+5V/3.3V)

Ground

No Connect

30A179-00

REV. C

This document contains information on a product that is currently released

to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right

to change products or specifications herein without prior notice.

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