DRC-10520
HIGH POWER 16-BIT D/R CONVERTER
FEATURES
signal output. A logic “0” BIT output
indicates an overcurrent condition in
the sine or cosine outputs. Reference
inputs are scalable with external
resistors. Loss of the reference signal
will not damage the converter.
DESCRIPTION
The DRC-10520 is a 16 bit, 32 pin
triple DIP D/R converter with 2 VA
drive capability. It features a power
amplifier that may be driven by a stan-
dard ±15 VDC power supply or by the
reference source (when used with the
optional power transformer DDC/PN
29306). The DRC-10520 provides
compatibility with microprocessors
through its 8-bit 2-byte transparent
input latch. Data input is natural bina-
ry angles in TTL compatible parallel
positive logic format.
The DRC-10520 is comprised of a
high accuracy D/R converter and a
dual power amplifier stage that has
high accuracy and low scale factor
variation. In addition, a standard BIT
circuit provides a digital overcurrent
•
2 VA Drive Capacity
•
8-Bit/2-Byte Double Buffered
Transparent Latch
APPLICATION
The DRC-10520 can be used where
digitized shaft angle data must be
converted to an analog format for dri-
ving control transformers. With its
built-in input latches, the DRC-10520
is especially compatible with a micro-
processor-based system including
flight simulators, flight instrumenta-
tion, fire control systems, radar and
navigation systems, and air data com-
puters.
•
Resolution: 16 Bits
Accuracy: to 1 Minute
•
Power Amplifier Uses AC
Reference or DC Supplies
•
BIT Output
+15 V DC
-15 V DC
DRC-10520
+V
OR
+15
-V
OR
-15
RH
RL
D/R
CONVERTER
HIGH ACCURACY
LOW SCALE FACTOR
VARIATION
S
DUAL
HI POWER
AMPLIFIERS
SIN
OPTIONAL
SCOTT-T
TRANSFORMER
SYNCHRO
OUTPUT
C
COS
BIT
BIT 1-16
TRANSPARENT
LATCH
TRANSPARENT
LATCH
LOGIC "0" INDICATES
OVER CURRENT
LM
LA
BITS 1-8 BITS 9-16
LL
DRC-10520 BLOCK DIAGRAM
©
1985, 1999 Data Device Corporation
TABLE 1. DRC-10520 SPECIFICATIONS
Apply over temperature range power supply ranges reference voltage
and frequency range and 10% harmonic distortion in the reference.
PARAMETER
RESOLUTION
ACCURACY AND
DYNAMICS
Output Accuracy
Without Scott-T
With Scott-T P/N29305
Differential Linearity
Output Settling Time
DIGITAL INPUT
Logic Type
16 bits
VALUE
TECHNICAL INFORMATION INTRODUCTION
The DRC-10520 is a digital-to-resolver (D/R) converter which
has an inherently high accuracy and low scale factor variation.
The circuit is based on an algorithm whose theoretical math error
is only ±3.5 arc seconds and whose theoretical scale factor vari-
ation with angle is less than ±0.015%. Therefore accuracy and
scale factor are limited only by the physical components, not by
the algorithm.
The digital inputs are CMOS double buffered transparent latches
(FIGURE 1). Angular output is determined by adding bits in the
logic 1 state.
±1 or ±4 minutes
±10 minutes (1.5 VA min for CT load)
±16 minutes (2 VA min for CT load)
±1 LSB
Less than 40 µsec for any digital input
step change
Natural binary angle parallel positive logic
CMOS and TTL compatible.
Inputs are CMOS transient protected.
Logic 0 = 0 to +1.25 V
Logic 1 = 2 V to 5 V
20 µA max to GND (bit 1-16)
20 µA max to V
L
(LL LM LA)
See Timing Diagram (FIGURE 2 ).
Differential 3.4 V rms
Higher voltages are scaled by adding
series resistors
DC to 1 kHz
13 kΩ ±0.5%
26 kΩ ±0.5%
Resolver
300 mA rms min (2 VA min)
REFERENCE LEVEL ADJUSTMENT
The input is specified for operation at a reference level of 3.4 V
rms; however, reference levels other than 3.4 V rms may be
scaied by calculating the value of the scaling resistor with the fol-
lowing equation:
R
REF
=
(V
REF
- 3.4)
x 13k
3.4
(26 - 3.4)
x 13k
3.4
Logic Voltage level
Load Current
Timing
REFERENCE INPUT
Type
Voltage
Frequency
Input Impedance
Single Ended
Differential
ANALOG OUTPUT
Type
Output Current
Max Output Voltage (tracks
reference input voltage)
Scale Factor Variation
eg., if V
REF
= 26 V rms, then R
REF
=
R
REF
INPUT
REF
RH
DRC-10520
RL
R REF
DC Offset (each line to
ground)
Protection
6.8 V rms max line-to-line ±1%
Simultaneous amplitude variation in all
output lines as function of digital angle is
±0.1% max.
±15 mV max varies with input angle.
Output is protected from overcurrent short
circuits and voltage feedback transients.
+15 V
+5%
+V
-V
20 V peak max
3 V above output
voltage min.
-18 V
+25 V
-25 V
20 mA load dependent
max
-15 V
+5%
The output is 6.8 V rms line-to-line resolver format signal which
may be converted into a synchro format of 11.8 V Iine-to-line with
the companion Scott-T transformer module available as DDC
P/N 29305.
DRIVING THE POWER AMPLIFIER WITH THE
REFERENCE
The high power amplifier stage can be driven by a standard ±15 V
DC supply or with a high efficiency pulsating power supply
derived from the reference voltage source. A companion power
transformer DDC P/N 29306, designed to implement the pulsat-
ing power source for the DRC-10520, is also available (FIGURE
3). The DRC-10520 will not be damaged by sequencing order in
the ±15 V, V
L
supplies or the reference input.
POWER SUPPLIES
Voltage
Voltage Limits
Max Voltage Without Damage
Current
Peak Current At Power Turn
On or Short Circuit (when
using Transformer)
TEMPERATURE RANGES
Operating (-3xx)
(-1xx)
Storage
PHYSICAL
CHARACTERISTICS
Package Type
Size
Weight
+18 V
20 mA
max
700 mA max
200 ns min.
0°C to +70°C case
-55°C to +125°C case
-55°C to +135°C
TRANSPARENT
LATCHED
DATA 1-16 BITS
32 pin triple DIP
1.14 x 1.74 x 0.18 inch (29 x 44 x 4 mm)
1.15 oz (33 g)
,,,,
,,,,,
50 ns min.
100 ns min.
FIGURE 2. LL, LM, LA TIMING DIAGRAM
2
OUTPUT PROTECTION AND BIT
The output is protected from overcurrent, short circuits and volt-
age feedback transients. The BIT circuit detects overcurrent con-
ditions in the sine or cosine resolver output. A logic “0” is used for
overcurrent detection. Normal operation is logic “1.” The BIT line
is normally at logic “1.” An overload or short circuit will cause the
BIT line to drop after 1 sec when the output current exceeds a
peak level of approximately 450 mA.
THERMAL CONSIDERATIONS
The power stage consists of two power amplifiers: one for the
sine output and one for the cosine output. Maximum power stage
junction temperature rise occurs at 0° and 180° for the sine out-
put and 90° and 270° for the cosine output.
Maximum power dissipation for the hybrid occurs at the
interquadrant points: 45°, 135°, 225°, and 315°. At these points
the total power dissipation of each amplifier is 0.707 max.
Therefore, the total power dissipation is 1.41 times the max for
any one amplifier.
The thermal resistance junction to the outside of the case is
10.6°C/W. For a 2 VA purely inductive load and ±15 VDC power
supplies, the junction temperature rise is 42°C. For a real induc-
tive load (one that has some power dissipation) and using pul-
sating supplies, the power dissipated is cut in half. The tempera-
ture rise is also halved to 21°C.
TABLE 2. PIN CONNECTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
FUNCTION
N.C.
N.C.
16 (LSB)
COS
DIN
+V
-V
1 (MSB)
2
3
4
PIN
12
13
14
15
16
17
18
19
20
21
22
FUNCTION
5
6
7
8
LM
LL
9
10
11
12
13
PIN
23
24
25
26
27
28
29
30
31
32
FUNCTION
14
R
L
R
H
15
-15 V
GND
LA
+15 V
BIT
N.C.
OUTPUT PHASING AND OUTPUT SCALE FACTOR
The analog output signals have the following phasing:
sin = (R
H
-R
L
) A
O
[1 + A (θ)] sin
θ
cos = (R
H
-R
L
) A
O
[1 + A (θ)] cos
θ
The output amplifiers simultaneously track reference voltage
fluctuations because they are proportional to (R
H
-R
L
). The ampli-
tude factor A
O
is 2 for 6.8 V rms L-L output. The maximum varia-
tion in A
O
from all causes is 0.3%. The term A (θ) represents the
variation of the amplitude with the digital input angle. A (θ),
which is called the scale factor variation, is a smooth function of
θ
without discontinuities and is less than ±0.1% for all values of
θ.
The total maximum variation in A
O
[1 + A (θ)] is therefore
±0.4%.
Because the amplitude factor (R
H
-R
L
) A
O
[1 + A (θ)] varies simul-
taneously on all output lines, it will not be a source of error when
the DRC-10520 is to drive a ratiometric system such as a
resolver or synchro. However, if the outputs are used indepen-
dently, as in x-y plotters, the amplitude variations must be taken
into account.
6
3.4 Vrms
7
3
REFERENCE
SOURCE
400 Hz
2
21.6 Vrms
C.T.
4
C-1
R
+
L
R
H
+SIN
1
6.8 Vrms
2
GND
+
C-2
-V
+COS
4
S
5
8
6
1
S
1
+V
DRC-10520
(SYNCHRO ONLY)
35 V DC
T-1
29306
33920
5
D1
D4
D2
D3
S
3
S
4
(RESOLVER
ONLY)
3
T-2
R 7
S
2
PARTS LIST FOR 400 Hz
For T1 and T2 see Ordering Information
D1, D2, D3, and D4 = 1N4245
C-1 and C-2 = 22 µF, 35 V DC capacitor
DIGITAL INPUT
29305
32976
*29947 RESOLVER
±15 V
FIGURE 3. TYPICAL CONNECTION DIAGRAM UTILIZING PULSATING
POWER SOURCE FOR SYNCHRO OUTPUT
3
1.00 MAX
(25.4)
0.800 ±0.005
(20.32 ±0.13)
0.700 ±0.010
(17.78 ±0.25)
3
TYP
32
0.050 TYP
(1.27)
0.100 TYP
(2.54)
TOL NON-CUM
(3)
(4)
0.90 MAX
(22.86)
0.600 ±0.010
(15.24 ±0.25)
(2)
PIN 8, 29947 ONLY
0.100 TYP
(2.54)
TOL NON-CUM
1.90 MAX
(48.26)
1.700 ±0.010
(43.18 ±0.25)
1.600 ±0.010
(40.64 ±0.25)
0.02 TYP
(0.51)
0.050 TYP
(1.27)
5
TYP
32
0.300
(7.62)
(1)
(5)
(6)
(1)
(7)
BOTTOM VIEW
(8)
0.20
(5.08)
5
TYP
32
0.40
(10.16)
0.90 MAX
(22.86)
(5)
BOTTOM VIEW
(6)
(7)
(2)
(3)
(4)
0.600 ±0.010
(15.24 ±0.25)
TERMINALS 0.020 ±0.002 (0.51 ±0.05)
x 0.187 MIN LG. BRASS SOLDER PLATED
4-40 INSERT
6 INTERNAL THREADS
TERMINALS 0.020 ±0.002 (0.51 ±0.05)
x 0.187 MIN LG. BRASS SOLDER PLATED
4-40 INSERT
6 INTERNAL THREADS
SIDE VIEW
0.52 MAX
(13.21)
SIDE VIEW
0.52 MAX
(13.21)
FIGURE 4. POWER TRANSFORMER
(29306, 33920) MECHANICAL OUTLINE
FIGURE 5. OUTPUT SCOTT-T TRANSFORMERS
(29305, 29947, 32976) MECHANICAL OUTLINE
TABLE 3. TRANSFORMER INFORMATION
POWER TRANSFORMER
SCOTT-T TRANSFORMER
29306
33920
29305
29947
32976
400 Hz ±10% for all transformers
26 V
see note 1
note 2
––
2 VA for all transformers
115 V
6.8 V
6.8 V
see note 1
note 2
––
Synchro
11.8 V L-L
––
1.1 VA 6 min;
2.0 VA 12 min
Resolver
11.8 V L-L
––
2.0 VA
2 min
6.8 V
Synchro
90 V L-L
––
1.1 VA
4 min
500 Vrms
@ 60 Hz
2.0 oz.
Freq. Range
Drive
Input (1-2)
Output
Phase Shift
Rated Load
(over -55 to +125°C)
Dielectric
250 Vrms
500 Vrms
500 Vrms
500 Vrms
withstanding volt.
@ 60 Hz
@ 60 Hz
@ 60 Hz
@ 60 Hz
(between windings)
Weight
1 oz.
1 oz.
2.0 oz.
2.0 oz.
Notes:
1. (3-4-5) 20.68 volts Centertapped, 7.5% Regualtion over temperature range.
(6-7) 3.4 volts, 5% Regulation over temperature range.
2. Max from winding 1-2 to 6-7 is 5° for ambient temperature -55 to +125°C.
4
1.140
(28.96)
0.900
(22.86)
16
17
0.250 MIN
(6.35)
0.175 MAX
(4.45)
1.740
(44.20)
15 EQ. SP.
0.100 = 1.500
TOL NUN-CUM
(2.54 = 38.1)
1
32
0.120 ±0.002 0.120 ±0.002
(3.05 ±0.05) (3.05 ±0.05)
BOTTOM
VIEW
0.018 ±0.002 DIA (TYP)
(0.46 ±0.05)
SIDE
VIEW
NOTES:
1. Dimensions shown are in inches (millimeters)
2. Lead identification numbers are for reference only.
3. Lead cluster shall be centered within ±0.010 (±2.54) of outline dimensions.
Lead spacing dimensions apply only at seating plane.
4. Pin material meets solderability requirements of MIL-PRF-38534, Method 2003.
5. Tol ±0.005 (±0.13) unless otherwise noted.
FIGURE 6. DRC-10520 MECHANICAL OUTLINE (32 PIN TRIPLE DIP)
5
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