MT58V1MV18PB-6 datasheet, PDF - EEWORLD Datasheet

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MT58V1MV18PB-6: DescriptionCache SRAM, 1MX18, 3.5ns, CMOS, PBGA119, PLASTIC, MS-028BHA, BGA-119; Categorystorage storage; File Size709KB，47 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT58V1MV18PB-6 Overview

Cache SRAM, 1MX18, 3.5ns, CMOS, PBGA119, PLASTIC, MS-028BHA, BGA-119

MT58V1MV18PB-6 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Parts packaging code	BGA
package instruction	PLASTIC, MS-028BHA, BGA-119
Contacts	119
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	3.5 ns
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	18874368 bit
Memory IC Type	CACHE SRAM
memory width	18
Number of functions	1
Number of terminals	119
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	2.4 mm
Maximum standby current	0.01 A
Minimum standby current	2.38 V
Maximum slew rate	0.475 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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ADVANCE

‡

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

18Mb SYNCBURST

™

SRAM

FEATURES

• Fast clock and OE# access times

• Single +3.3V ±0.165V or +2.5V ±0.125V power supply

)

• Separate +3.3V or +2.5V isolated output buffer supply

• SNOOZE MODE for reduced-power standby

• Single-cycle deselect (Pentium

BSRAM-compatible)

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL WRITE

• Three chip enables for simple depth expansion and

address pipelining

• Clock-controlled and registered addresses, data I/Os,

and control signals

• Internally self-timed WRITE cycle

• Burst control (interleaved or linear burst)

• Automatic power-down for portable applications

• Low capacitive bus loading

• x18, x32, and x36 versions available

MT58L1MY18P, MT58V1MV18P,

MT58L512Y32P, MT58V512V32P,

MT58L512Y36P, MT58V512V36P

3.3V V

, 3.3V or 2.5V I/O; 2.5V V

, 2.5V

I/O, Pipelined, Single-Cycle Deselect

100-Pin TQFP

165-Pin FBGA

OPTIONS

• Timing (Access/Cycle/MHz)

2.5V V

, 2.5V I/O

3.5ns/6ns/166 MHz

4.0ns/7.5ns/133 MHz

5ns/10ns/100 MHz

3.3V V

, 3.3V or 2.5V I/O

4.0ns/7.5ns/133 MHz

5ns/10ns/100 MHz

• Configurations

3.3V V

, 3.3V or 2.5V I/O

1 Meg x 18

512K x 32

512K x 36

2.5V V

, 2.5V I/O

1 Meg x 18

512K x 32

512K x 36

• Packages

100-pin TQFP (3-chip enable)

165-pin FBGA

119-pin BGA

• Operating Temperature Range

Commercial (0ºC to +70ºC)

MARKING

-6

-7.5

-10

-7.5

-10

119-Pin BGA

MT58L1MY18P

MT58L512Y32P

MT58L512Y36P

MT58V1MV18P

MT58V512V32P

MT58V512V36P

None

* A Part Marking Guide for the FBGA devices can be found on Micron’s

Web site—http://www.micron.com/support/index.html.

NOTE:

1. JEDEC-standard MS-026 BHA (LQFP).

2. JEDEC-standard MS-028 BHA (PBGA).

Part Number Example:

MT58L1MY18PT-6

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined, SCD SyncBurst SRAM

MT58L1MY18P_C.p65 – Rev. C; Pub. 9/01

AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE

BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

‡

PRODUCTS

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