Data Sheet
FEATURES
AD5301:
buffered voltage output 8-bit DAC
AD5311:
buffered voltage output 10-bit DAC
AD5321:
buffered voltage output 12-bit DAC
6-lead SOT-23 and 8-lead MSOP packages
Micropower operation: 120 μA at 3 V
2-wire (I
2
C-compatible) serial interface
Data readback capability
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 50 nA at 3 V
Reference derived from power supply
Power-on reset to 0 V
On-chip rail-to-rail output buffer amplifier
3 power-down functions
2.5 V to 5.5 V, 120 μA, 2-Wire Interface,
Voltage-Output 8-/10-/12-Bit DACs
AD5301/AD5311/AD5321
GENERAL DESCRIPTION
The
AD5301/AD5311/AD5321
1
are single 8-/10-/12-bit, buff-
ered, voltage-output DACs that operate from a single 2.5 V to
5.5 V supply, consuming 120 μA at 3 V. The on-chip output
amplifier allows rail-to-rail output swing with a slew rate of
0.7 V/μs. It uses a 2-wire (I
2
C-compatible) serial interface that
operates at clock rates up to 400 kHz. Multiple devices can share
the same bus.
The reference for the DAC is derived from the power supply
inputs and thus gives the widest dynamic output range. These
devices incorporate a power-on reset circuit, which ensures that
the DAC output powers up to 0 V and remains there until a
valid write takes place. The devices contain a power-down
feature that reduces the current consumption of the device to
50 nA at 3 V and provides software-selectable output loads
while in power-down mode.
The low power consumption in normal operation makes these
DACs ideally suited to portable battery-operated equipment. The
power consumption is 0.75 mW at 5 V and 0.36 mW at 3 V,
reducing to 1 μW in all power-down modes.
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAM
V
DD
SCL
SDA
INTERFACE
LOGIC
A0
A1*
AD5301/AD5311/AD5321
REF
DAC
REGISTER
8-/10-/12-BIT
DAC
BUFFER
V
OUT
POWER-DOWN
LOGIC
RESISTOR
NETWORK
POWER-ON
RESET
GND
*AVAILABLE ON 8-LEAD VERSION ONLY
PD*
Figure 1.
1
Protected by U.S. Patent No. 5684481.
Document Feedback
Rev. C
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1999–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
00927-001
AD5301/AD5311/AD5321
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 13
Digital-to-Analog ....................................................................... 13
Resistor String ............................................................................. 13
Data Sheet
Output Amplifier........................................................................ 13
Power-On Reset .......................................................................... 13
Serial Interface ................................................................................ 14
2-Wire Serial Bus ........................................................................ 14
Input Shift Register .................................................................... 14
Write Operation.......................................................................... 15
Read Operation........................................................................... 16
Power-Down Modes .................................................................. 17
Applications Notes ......................................................................... 18
Using the REF193/REF195 as a Power Supply ........................ 18
Bipolar Operation Using the AD5301/ AD5311/AD5321 .... 18
Multiple Devices on One Bus ................................................... 18
CMOS Driven SCL and SDA Lines.......................................... 18
Power Supply Decoupling ......................................................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 21
REVISION HISTORY
6/2016—Rev. B to Rev. C
Changes to Figure 33 and Figure 34 ............................................. 16
Changes to Ordering Guide .......................................................... 22
3/2007—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Table 4 ............................................................................ 6
Changes to Figure 4 Caption ........................................................... 7
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
11/2003—Rev. 0 to Rev. A
Changes to Ordering Guide ............................................................ 4
Updated Outline Dimensions ....................................................... 15
7/1999—Revision 0: Initial Version
Rev. C | Page 2 of 24
Data Sheet
SPECIFICATIONS
AD5301/AD5311/AD5321
V
DD
= 2.5 V to 5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
2
DC PERFORMANCE
3, 4
AD5301
Resolution
Relative Accuracy
Differential Nonlinearity
AD5311
Resolution
Relative Accuracy
Differential Nonlinearity
AD5321
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
5
Gain Error Drift
5
OUTPUT CHARACTERISTICS
5
Minimum Output Voltage
Maximum Output Voltage
DC Output Impedance
Short-Circuit Current
Power-Up Time
LOGIC INPUTS (A0, A1, PD)
5
Input Current
Input Low Voltage, V
IL
Min
B Version
1
Typ
Max
Unit
Test Conditions/Comments
8
±0.15
±0.02
10
±0.5
±0.05
12
±2
±0.3
5
±0.15
±0.15
–20
−5
±1
±0.25
Bits
LSB
LSB
Bits
LSB
LSB
Bits
LSB
LSB
mV
% of FSR
% of FSR
μV/°C
ppm of
FSR/°C
V
V
Ω
mA
mA
μs
μs
Guaranteed monotonic by design over all codes.
±4
±0.5
Guaranteed monotonic by design over all codes.
±16
±0.8
20
±1.25
±1
Guaranteed monotonic by design over all codes.
All zeros loaded to DAC, see Figure 12.
All ones loaded to DAC, see Figure 12.
0.001
V
DD
− 0.001
1
50
20
2.5
6
±1
0.8
0.6
0.5
2.4
2.1
2.0
3
0.7 × V
DD
−0.3
0.05 × V
DD
6
50
V
DD
+ 0.3
+0.3 × V
DD
±1
This is a measure of the minimum drive capability of the
output amplifier.
This is a measure of the maximum drive capability of the
output amplifier.
V
DD
= 5 V.
V
DD
= 3 V.
Coming out of power-down mode. V
DD
= 5 V.
Coming out of power-down mode. V
DD
= 3 V.
Input High Voltage, V
IH
Pin Capacitance
LOGIC INPUTS (SCL, SDA)
5
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Leakage Current, I
IN
Input Hysteresis, V
HYST
Input Capacitance, C
IN
Glitch Rejection
6
μA
V
V
V
V
V
V
pF
V
V
μA
V
pF
ns
V
DD
= 5 V ± 10%.
V
DD
= 3 V ± 10%.
V
DD
= 2.5 V.
V
DD
= 5 V ± 10%.
V
DD
= 3 V ± 10%.
V
DD
= 2.5 V.
V
IN
= 0 V to V
DD
.
Pulse width of spike suppressed.
Rev. C | Page 3 of 24
AD5301/AD5311/AD5321
Parameter
2
LOGIC OUTPUT (SDA)
5
Data Sheet
B Version
1
Typ
Max
0.4
0.6
±1
6
Unit
V
V
μA
pF
Test Conditions/Comments
I
SINK
= 3 mA.
I
SINK
= 6 mA.
Min
Output Low Voltage, V
OL
Three-State Leakage
Current
Three-State Output
Capacitance
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
I
DD
(Power-Down Mode)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
1
2
2.5
150
120
0.2
0.05
5.5
250
220
1
1
V
μA
μA
μA
μA
I
DD
specification is valid for all DAC codes.
DAC active and excluding load current.
V
IH
= V
DD
and V
IL
= GND.
V
IH
= V
DD
and V
IL
= GND.
V
IH
= V
DD
and V
IL
= GND.
V
IH
= V
DD
and V
IL
= GND.
Temperature range is as follows: B Version: −40°C to +105°C.
See the Terminology section.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range:
AD5301
(Code 7 to 250);
AD5311
(Code 28 to 1000); and
AD5321
(Code 112 to 4000).
5
Guaranteed by design and characterization, not production tested.
6
Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Rev. C | Page 4 of 24
Data Sheet
AC CHARACTERISTICS
1
AD5301/AD5311/AD5321
V
DD
= 2.5 V to 5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
3
Output Voltage Settling Time
AD5301
AD5311
AD5321
Slew Rate
Major-Code Change Glitch Impulse
Digital Feedthrough
1
2
B Version
2
Min
Typ
Max
6
7
8
0.7
12
0.3
8
9
10
Unit
μs
μs
μs
V/μs
nV-s
nV-s
Test Conditions/Comments
V
DD
= 5 V
1/4 scale to 3/4 scale change (0x40 to 0xC0)
1/4 scale to 3/4 scale change (0x100 to 0x300)
1/4 scale to 3/4 scale change (0x400 to 0xC00)
1 LSB change around major carry
See the Terminology section.
Temperature range for the B Version is as follows: –40°C to +105°C.
3
Guaranteed by design and characterization, not production tested.
TIMING CHARACTERISTICS
1
V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
2
f
SCL
t
1
t
2
t
3
t
4
t
5
t
63
t
7
t
8
t
9
t
10
t
11
Limit at T
MIN
,
T
MAX,
B Version
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
300
20 + 0.1C
b5
400
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns max
ns min
pF max
Test Conditions/Comments
SCL clock frequency
SCL cycle time
t
HIGH
, SCL high time
t
LOW
, SCL low time
t
HD,STA
, start/repeated start condition hold time
t
SU,DAT,
data setup time
t
HD,DAT
, data hold time
t
SU,STA
, setup time for repeated start
t
SU,STO
, stop condition setup time
t
BUF
, bus free time between a stop condition and a start condition
t
R
, rise time of both SCL and SDA when receiving
4
May be CMOS driven
t
F
, fall time of SDA when receiving
4
t
F
, fall time of both SCL and SDA when transmitting
4
Capacitive load for each bus line
C
b
1
2
See Figure 2.
Guaranteed by design and characterization, not production tested.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (refer to the V
IH MIN
of the SCL signal) in order to bridge the undefined region of the
falling edge of the SCL.
4
t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
5
C
b
is the total capacitance of one bus line in picofarads.
SDA
t
9
SCL
t
3
t
10
t
11
t
4
t
4
START
CONDITION
t
6
t
2
t
5
t
7
REPEATED
START
CONDITION
t
1
t
8
00927-002
STOP
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. C | Page 5 of 24
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