provides 14 outputs partitioned in 3 banks of 5, 5, and 4
outputs. Bank A and Bank B divide the VCO output by 4
or 8 while Bank C divides by 8 or 12 per SEL(A:C)
settings, see
Functional Table.
These dividers allow
output to input ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1,
and 2:3. Each LVCMOS compatible output can drive 50Ω
series or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one
or two traces giving the device an effective fanout of 1:28.
The PLL is ensured stable, given that the VCO is
configured to run between 200MHz and 500MHz. This
allows a wide range of output frequencies from 8.3MHz to
200MHz. For normal operation, the external feedback
input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the
input reference clock set by the feedback divider, see
Frequency Table.
When PLL_EN is LOW, PLL is
bypassed and the reference clock directly feeds the
output dividers. This mode is fully static and the minimum
input clock frequency specification does not apply.
Functional Description
The PCS5I9775 is a low-voltage high-performance
200MHz PLL-based zero delay buffer designed for
high-speed
clock
distribution
applications.
The
PCS5I9775 features two reference clock inputs and
Block Diagram
.
VCO_SEL (1, 0)
PLL_EN
TCLK_SEL
TCLK0
TCLK1
FB_IN
SELA
÷2/÷4
CLK
STOP
÷2
PLL
200-
500MHZ
÷2/÷4
÷4
CLK
STOP
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QB4
SELB
÷4/÷6
SELC
CLK_STP#
CLK
STOP
QC0
QC1
QC2
QC3
FB_OUT
÷4/÷6/÷8/÷12
FB_SEL(1.0)
MR#/OE
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006
rev 0.4
Pin Configuration
PCS5I9775
VCO_SEL
VDDQC
VDDQC
VDDQB
QC1
QC2
QC3
VSS
VSS
QC0
VSS
VSS
MR#/OE
CLK_STP#
SELB
SELC
PLL_EN
SELA
TCLK_SEL
TCLK0
TCLK1
VCO_SEL1
VDD
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
52 51 50 49 48 47 46 45 44 43 42 41 40
NC
QB0
39
38
37
36
35
34
33
32
31
30
29
28
27
VSS
QB1
VDDQB
QB2
VSS
QB3
VDDQB
QB4
FB_IN
VSS
FB_OUT
VDDFB
NC
PCS5I9775
14 15 16 17 18 19 20 21 22 23 24 25 26
QA3
QA2
QA1
QA4
FB_SEL0
FB_SEL1
VSS
AVSS
VDDQA
VDDQA
VSS
QA0
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
VDDQA
2 of 12
September 2006
rev 0.4
Pin
9
10
16, 18,
21, 23,
25
32, 34,
36, 38,
40
44, 46,
48, 50
29
31
2
3
6
8
11, 52
7, 4, 5
20, 14
17, 22,
26
33, 37,
41
45, 49
28
13
12
15
1, 19,
24, 30,
35, 39,
43, 47,
51
27, 42
PCS5I9775
I/O
I, PD
I, PU
O
O
O
O
I, PU
I, PU
I, PU
I, PU
I, PD
I, PD
I, PD
I, PD
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Pin Description
1
Name
TCLK0
TCLK1
QA(4:0)
QB(4:0)
QC(3:0)
FB_OUT
FB_IN
MR#/OE
CLK_STP#
PLL_EN
TCLK_SEL
VCO_SEL(1,0)
SEL(A:C)
FB_SEL(1,0)
VDDQA
VDDQB
VDDQC
VDDFB
AVDD
VDD
AVSS
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VDD
VDD
VDD
VDD
VDD
VDD
Ground
Description
LVCMOS/LVTTL reference clock input
LVCMOS/LVTTL reference clock input
Clock output bank A
Clock output bank B
Clock output bank C
Feedback clock output.
Connect to FB_IN for normal operation.
Feedback clock input.
Connect to FB_OUT for normal operation.
This input should be at the same voltage rail as input reference
clock. See
Table 1.
Output enable/disable input.
See
Table 2.
Clock stop enable/disable input.
See
Table 2.
PLL enable/disable input.
See
Table 2.
Reference select input.
See
Table 2.
VCO divider select input.
See
Tables 2, 3 and 4.
Frequency select input, Bank (A:C).
See
Table 3.
Feedback dividers select inputs.
See
Table 4.
2.5V or 3.3V Power supply for bank A output clocks
2,3
2.5V or 3.3V Power supply for bank B output clocks
2,3
2.5V or 3.3V Power supply for bank C output clocks
2,3
2.5V or 3.3V Power supply for feedback output clock
2,3
2.5V or 3.3V Power supply for PLL
2,3
2.5V or 3.3V Power supply for core and inputs
2,3
Analog Ground
VSS
Supply
Ground
Common Ground
NC
No Connection
Notes:
1. PU = Internal pull-up, PD = Internal pull-down
2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power
supply pins.
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 12
September 2006
rev 0.4
‘SpreadTrak’
Many systems being designed now utilize a technology
called Spread Spectrum Frequency Timing Generation.
PCS5I9975A is designed so as not to filter off the Spread
Spectrum feature of the Reference Input, assuming it
exists.
PCS5I9775
When a zero delay buffer is not designed to pass the
Spread Spectrum feature through, the result is a significant
amount of tracking skew which may cause problems in the
systems requiring synchronization.
Table 1. Frequency Table
Feedback Output
Divider
÷8
÷12
÷16
÷24
÷32
÷48
÷4
÷6
÷8
÷12
VCO
Input Clock * 8
Input Clock * 12
Input Clock * 16
Input Clock * 24
Input Clock * 32
Input Clock * 48
Input Clock * 4
Input Clock * 6
Input Clock * 8
Input Clock * 12
Input Frequency Range
(AVDD = 3.3V)
25MHz to 62.5MHz
16.6MHz to 41.6MHz
12.5MHz to 31.25MHz
8.3MHz to 20.8MHz
6.25MHz to 15.625MHz
4.2MHz to 10.4MHz
50MHz to 125MHz
33.3MHz to 83.3MHz
25MHz to 62.5MHz
16.6MHz to 41.6MHz
Input Frequency Range
(AVDD = 2.5V)
25MHz to 50MHz
16.6MHz to 33.3MHz
12.5MHz to 25MHz
8.3MHz to 16.6MHz
6.25MHz to 12.5MHz
4.2 MHz to 8.3MHz
50MHz to 100MHz
33.3MHz to 66.6MHz
25MHz to 50MHz
16.6MHz to 33.3MHz
Table 2. Function Table (Configuration controls)
Control
TCLK_SEL
VCO_SEL0
VCO_SEL1
PLL_EN
Default
0
0
0
1
TCLK0
0
TCLK1
VCO÷2 (mid input frequency range)
Gated by VCO_SEL0
Bypass mode, PLL disabled. The input clock
connects to the output dividers
Outputs disabled (three-state) and reset of the
device. During reset/output disable the PLL
feedback loop is open and the VCO running at its
minimum frequency. The device is reset by the
internal power-on reset (POR) circuitry during
power-up.
QA, QB, and QC outputs disabled in LOW state.
FB_OUT is not affected by CLK_STP.
1
VCO÷4 (low input frequency range)
VCO (high input frequency range)
PLL enabled. The VCO output
connects to the output dividers
MR/OE
1
Outputs enabled
CLK_STP
1
Outputs enabled
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 12
September 2006
rev 0.4
Table 3. Function Table (Bank A, B, and C)
VCO_SEL1
0
0
0
0
1
1
PCS5I9775
VCO_SEL0
0
0
1
1
x
x
SELA
0
1
0
1
0
1
QA(4:0)
÷4
÷8
÷8
÷16
÷2
÷4
SELB
0
1
0
1
0
1
QB(4:0)
÷4
÷8
÷8
÷16
÷2
÷4
SELC
0
1
0
1
0
1
QC(3:0)
÷8
÷12
÷16
÷24
÷4
÷6
Table 4. Function Table (FB_OUT)
VCO_SEL1
0
0
0
0
0
0
0
0
1
1
1
1
VCO_SEL0
0
0
0
0
1
1
1
1
x
x
x
x
FB_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
FB_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
FB_OUT
÷8
÷16
÷12
÷24
÷16
÷32
÷24
÷48
÷4
÷8
÷6
÷12
Absolute Maximum Conditions
Parameter
VDD
VDD
V
IN
V
OUT
V
TT
LU
R
PS
T
S
T
A
T
J
Ø
JC
Ø
JA
ESD
H
FIT
Description
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Latch Up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
Condition
Functional
Relative to VSS
Relative to VSS
Functional
Ripple Frequency < 100kHz
Non Functional
Functional
Functional
Functional
Functional
Manufacturing test
Min
-0.3
2.375
-0.3
-0.3
200
-65
-40
Max
5.5
3.465
VDD+ 0.3
VDD+ 0.3
VDD ÷2
150
+150
+85
150
23
55
10
Unit
V
V
V
V
V
mA
mVp-p
°C
°C
°C
°C/W
°C/W
Volts
ppm
2000
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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Embedded System
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