Product Specification
PE43503
Product Description
The PE43503 is a HaRP™-enhanced, high linearity, 5-bit RF
Digital Step Attenuator (DSA) covering a 31 dB attenuation
range in 1 dB steps. The Peregrine 50Ω RF DSA provides a
serial CMOS control interface. It maintains high attenuation
accuracy over frequency and temperature and exhibits very low
insertion loss and low power consumption. Performance does
not change with Vdd due to on-board regulator. This next
generation Peregrine DSA is available in a 4x4 mm 24-lead
QFN footprint.
The PE43503 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
50
Ω
RF Digital Attenuator
5-bit, 31 dB, DC-6.0 GHz
Features
•
HaRP™-enhanced UltraCMOS™ device
•
Attenuation: 1 dB steps to 31 dB
•
High Linearity: Typical +58 dBm IP3
•
Excellent low-frequency performance
•
3.3 V or 5.0 V Power Supply Voltage
•
Fast switch settling time
•
Programming Modes:
•
•
•
Direct Parallel
Latched Parallel
Serial
•
High-attenuation state @ power-up (PUP)
•
CMOS Compatible
Figure 1. Package Type
24-lead 4x4x0.85 mm QFN Package
•
No DC blocking capacitors required
•
Packaged in a 24-lead 4x4x0.85 mm QFN
Figure 2. Functional Schematic Diagram
Switched Attenuator Array
RF Input
RF Output
Parallel Control
Serial In
5
Control Logic Interface
CLK
LE
A0
A1
A2
P/S
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
Document No. 70-0252-04
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PE43503
Product Specification
Table 1. Electrical Specifications @ +25°C, V
DD
= 3.3 V or 5.0 V
Parameter
Frequency Range
Attenuation Range
Insertion Loss
0dB - 31dB Attenuation settings
0dB - 21dB Attenuation settings
22dB - 31dB Attenuation settings
0dB - 31dB Attenuation settings
All States
Input
Two tones at +18 dBm, 20 MHz spacing
1 dB Step
DC
≤
6 GHz
DC
≤
4 GHz
4 GHz
≤
6 GHz
4 GHz
≤
6 GHz
4 GHz
≤
6 GHz
DC
≤
6 GHz
20 MHz - 6 GHz
20 MHz – 6 GHz
DC
≤
6 GHz
50% DC CTRL to 10% / 90% RF
1 MHz
30
72
32
+58
17
650
-115
10
10% / 90% RF
RF settled to within 0.05 dB of final value
RBW = 5 MHz, Averaging ON.
400
4
Test Conditions
Frequency
Min.
Typical
DC – 6
0 – 31
2.4
2.9
±(0.3+3%)
+0.4+9%
+2.4+0%
-0.2-3%
Max.
Units
GHz
dB
dB
dB
dB
dB
dB
°
dBm
dBm
dB
ns
dBm
mV
pp
ns
µs
Attenuation Error
Relative Phase
P1dB
Input IP3
Return Loss
Switching Speed
Typical Spurious Value
Video Feed Through
RF Trise/Tfall
Settling Time
Performance Plots
Figure 3. 1dB Step Error vs. Frequency *
1.6
1.4
1.2
Step Error (dB.)
1
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
Attenuation Setting (dB.)
Figure 4. 1dB Attenuation vs. Attenuation State
Attenuation
35
30
900 MHz
2200 MHz
3800 MHz
5800 MHz
200MHz
4000MHz
900MHz
5000MHz
1800MHz
6000MHz
2200MHz
Attenuation
(dB)
dB
25
20
15
10
5
0
0
5
10
15
20
25
30
35
*Monotonicity is held so long as Step-Error does not cross zero
Attenuation State
Figure 5. 1dB Major State Bit Error
1dB State
8dB State
2.00
1.50
1.00
Bit Error (dB.)
0.50
0.00
-0.50
-1.00
-1.50
-2.00
0.0
1.0
2.0
3.0
Frequency (GHz)
4.0
5.0
6.0
Figure 6. 1dB Attenuation Error vs. Frequency
2
1.5
1
Attenuation Error (dB.)
0.5
0
-0.5
-1
-1.5
-2
0
5
10
15
20
25
30
35
Attenuation Setting (dB.)
200MHz
4000MHz
2200MHz
5000MHz
3000MHz
6000MHz
2dB State
16dB State
4dB State
31dB State
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
Document No. 70-0252-04
│
UltraCMOS™ RFIC Solutions
PE43503
Product Specification
Figure 7. Insertion Loss vs. Temperature
-40C
0
-0.5
+25C
+85C
Figure 8. Input Return Loss vs. Attenuation
@ T = +25C
0
-5
Input Return Loss (dB.)
-10
-15
-20
-25
-30
-35
-40
0dB
4dB
0.5dB
8dB
1dB
16dB
2dB
31dB
Insertion Loss (dB)
-1
-1.5
-2
-2.5
-3
-3.5
0
2
4
6
8
10
Frequency (GHz.)
0
1
2
3
4
5
6
7
8
9
Frequency (GHz.)
Figure 9. Output Return Loss vs. Attenuation
@ T = +25C
0
-5
-10
Return Loss (dB.)
-15
-20
-25
-30
-35
-40
-45
0
1
2
3
4
5
6
7
8
9
Frequency (GHz.)
0dB
4dB
0.5dB
8dB
1dB
16dB
2dB
31dB
Figure 10. Relative Phase vs. Frequency
140
120
100
80
60
40
20
0
0
1
2
3
4
5
6
7
8
Frequency (GHz.)
0dB
8dB
1dB
16dB
2dB
31dB
4dB
Figure 11. Attenuation Error vs. Temperature
@ 6 GHz
-40C
2
1.5
Attenuation Error (dB.)
1
+25C
+85C
Figure 12. Input IP3 vs. Frequency
0dB
8dB
1dB
16dB
2dB
31dB
4dB
Relative Phase Error (Deg.)
70
65
60
Input IP3 (dBm.)
55
50
45
40
35
30
0
5
10
15
20
25
30
35
0.5
0
-0.5
-1
-1.5
-2
Attenuation Setting (dB.)
0
500
1000
1500
2000
2500
3000
3500
4000
4500
Frequency (MHz)
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Page 3 of 11
PE43503
Product Specification
Figure 13. Pin Configuration (Top View)
GND C1 C2 C4 C8 C16
24
NC
VDD
P/S
GND
RF1
GND
1
2
3
4
5
6
7
GND
8
GND
9
GND
10
GND
11
GND
12
GND
23
22
21
20
19
18
17
SI
CLK
LE
GND
RF2
GND
Table 3. Operating Ranges
Parameter
V
DD
Power Supply Voltage
V
DD
Power Supply Voltage
I
DD
Power Supply Current
Digital Input High
P
IN
Input power (50Ω):
1 Hz
≤
20 MHz
20 MHz
≤
4 GHz
T
OP
Operating temperature range
Digital Input Low
Digital Input Leakage
1
-40
0
25
2.6
Min
3.0
Typ
3.3
5.0
70
5.5
350
5.5
Fig. 14
+23
85
1
15
Max
Units
V
V
µA
V
dBm
dBm
°C
V
µA
Exposed
Solder Pad
16
15
14
13
Table 2. Pin Descriptions
Pin No.
1
2
3
4
5
6
7 - 12
13
14
15
16
17
18
19
20
21
22
23
24
Pin Name
NC
V
DD
P/S
GND
RF1
GND
GND
GND
RF2
GND
LE
CLK
SI
C16
C8
C4
C2
C1
GND
No Connect
Description
Power supply pin
Serial/Parallel mode select
Ground
RF1 port
Ground
Ground
Ground
RF2 port
Ground
Latch Enable input
Serial interface clock input
Serial Interface input
Attenuation control bit, 16 dB
Attenuation control bit, 8 dB
Attenuation control bit, 4 dB
Attenuation control bit, 2 dB
Attenuation control bit, 1 dB
Ground
Note 1. Input leakage current per Control pin
Table 4. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
ST
P
IN
V
ESD
Parameter/Conditions
Power supply voltage
Voltage on any Digital input
Storage temperature range
Input power (50Ω)
1 Hz
≤
20 MHz
20 MHz
≤
4 GHz
ESD voltage (HBM)
1
ESD voltage (Machine Model)
Min
-0.3
-0.3
-65
Max
6.0
5.8
150
Fig. 14
+23
500
100
Units
V
V
°C
dBm
dBm
V
V
Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Figure 14. Maximum Power Handling Capability
30.0
25.0
Ground C1 C2, C4, C8, C16 if not in use.
Exposed Solder Pad Connection
Pin dBm
20.0
15.0
10.0
The exposed solder pad on the bottom of the package
must be grounded for proper device
operation.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE43503 in
the 24-lead 4x4 QFN package is MSL1.
5.0
0.0
1.0E+03
1.0E+04
1.0E+05
1.0E+06
Hz
1.0E+07
1.0E+08
1.0E+09
Switching Frequency
The PE43503 has a maximum 25 kHz switching rate.
Switching rate is defined to be the speed at which the
DSA can be toggled across attenuation states.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating.
Document No. 70-0252-04
│
UltraCMOS™ RFIC Solutions
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
PE43503
Product Specification
Table 5. Control Voltage
State
Low
High
Bias Condition
0 to +1.0 Vdc at 2
µA
(typ)
+2.6 to +5 Vdc at 10
µA
(typ)
Table 6. Latch and Clock Specifications
Latch Enable
X
↑
Shift Clock
↑
X
Function
Shift Register Clocked
Contents of shift register
transferred to attenuator core
Table 7. Parallel Truth Table
Parallel Control Setting
D6
L
L
L
L
L
H
H
Table 8. Attenuation Word Truth Table
Attenuation Word
D7
X
X
X
X
X
X
X
D5
L
L
L
L
H
L
H
D4
L
L
L
H
L
L
H
D3
L
L
H
L
L
L
H
D2
L
H
L
L
L
L
H
Attenuation Setting
RF1-RF2
Reference I.L.
1 dB
2 dB
4 dB
8 dB
16 dB
31 dB
D6
L
L
L
L
L
H
H
D5
L
L
L
L
H
L
H
D4
L
L
L
H
L
L
H
D3
L
L
H
L
L
L
H
D2
L
H
L
L
L
L
H
D1
L
L
L
L
L
L
H
D0
(LSB)
L
L
L
L
L
L
H
Attenuation
Setting
RF1-RF2
Reference I.L.
1 dB
2 dB
4 dB
8 dB
16 dB
31 dB
Table 9. Serial Register Map
MSB (last in)
Q7
D7
Q6
D6
Q5
D5
Q4
D4
Q3
D3
Q2
D2
LSB (first in)
Q1
D1
Q0
D0
Bits can either be set to logic high or logic low
Attenuation Word
Attenuation Word is derived directly from the attenuation value. For example, to program the 13 dB state:
Attenuation Word: Multiply by 4 and convert to binary
→
4 *13 dB
→
52
→
X0110100
Serial Input: X0110100
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