8735AY-31 datasheet, PDF - EEWORLD Datasheet

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8735AY-31: DescriptionPLL Based Clock Driver, 8735 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC-HD, LQFP-32; Categorylogic logic; File Size787KB，21 Pages; ManufacturerIDT (Integrated Device Technology)

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8735AY-31 Overview

PLL Based Clock Driver, 8735 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC-HD, LQFP-32

8735AY-31 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC-HD, LQFP-32
Contacts	32
Reach Compliance Code	not_compliant
ECCN code	EAR99
series	8735
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	R-PQFP-G32
JESD-609 code	e0
length	7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	32
Actual output times	5
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP32,.35SQ,32
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Prop。Delay @ Nom-Sup	5.1 ns
propagation delay (tpd)	5.1 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.035 ns
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	7 mm
minfmax	15.625 MHz
Base Number Matches	1

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1:5, DIFFERENTIAL-TO-3.3V LVPECL

ZERO DELAY CLOCK GENERATOR

ICS8735-31

Features

•

Five differential 3.3V LVPECL output pairs

Selectable differential clock inputs

CLKx/nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

Output frequency range: 15.625MHz to 350MHz

Input frequency range: 15.625MHz to 350MHz

VCO range: 250MHz to 700MHz

External feedback for “zero delay” clock regeneration

with configurable frequencies

Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

Cycle-to-cycle jitter: 60ps (maximum)

Output skew: 35ps (maximum)

Static phase offset: 55ps ± 125ps

Full 3.3V supply voltage

0°C to 70°C ambient operating temperature

Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

General Description

The ICS8735-31 is a highly versatile 1:5 Differential

-to-3.3V LVPECL Clock Generator and a member of

HiPerClockS™

the HiPerClockS™ family of High Performance

Clock Solutions from IDT. The ICS8735-31 has a

fully integrated PLL and can be configured as zero

delay buffer, multiplier or divider, and has an output frequency

range of 15.625MHz to 350MHz. The reference divider, feedback

divider and output divider are each programmable, thereby

allowing for the following output-to-input frequency ratios: 8:1, 4:1,

2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to

achieve “zero delay” between the input clock and the output

clocks. The PLL_SEL pin can be used to bypass the PLL for

system test and debug purposes. In bypass mode, the reference

clock is routed around the PLL and into the internal output

dividers.

ICS

Block Diagram

PLL_SEL

Pullup

÷2, ÷4, ÷8, ÷16,

÷32

÷64, ÷128

nQ0

nQ1

nQ2

nQ3

nQ4

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

Pin Assignment

PLL_SEL

SEL3

CCA

CCO

nQ4

32 31 30 29 28 27 26 25

SEL0

SEL1

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

CLK0

Pulldown

nCLK0

Pullup

nCLK1

CLK1

Pulldown

Pullup

10 11 12 13 14 15 16

nFB_IN

FB_IN

SEL2

CCO

nQ0

CCO

nQ3

nQ2

nQ1

CCO

PLL

CLK_SEL

Pulldown

FB_IN

Pulldown

nFB_IN

Pullup

SEL0

Pulldown

SEL1

Pulldown

SEL2

Pulldown

SEL3

Pulldown

ICS8735-31

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

IDT™ / ICS™

3.3V LVPECL ZERO DELAY CLOCK GENERATOR

ICS8735AY-31 REV. B FEBRUARY 18, 2009

8735AY-31 Related Products

	8735AY-31	8735AY-31T
Description	PLL Based Clock Driver, 8735 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC-HD, LQFP-32	PLL Based Clock Driver, 8735 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC-HD, LQFP-32
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFP	QFP
package instruction	7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC-HD, LQFP-32	7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC-HD, LQFP-32
Contacts	32	32
Reach Compliance Code	not_compliant	not_compliant
ECCN code	EAR99	EAR99
series	8735	8735
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	R-PQFP-G32	R-PQFP-G32
JESD-609 code	e0	e0
length	7 mm	7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3	3
Number of functions	1	1
Number of terminals	32	32
Actual output times	5	5
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP
Encapsulate equivalent code	QFP32,.35SQ,32	QFP32,.35SQ,32
Package shape	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	240	240
power supply	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	5.1 ns	5.1 ns
propagation delay (tpd)	5.1 ns	5.1 ns
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.035 ns	0.035 ns
Maximum seat height	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	20	20
width	7 mm	7 mm
minfmax	15.625 MHz	15.625 MHz
Base Number Matches	1	1

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