1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values.
2
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CONTROL INPUT FUNCTION TABLE
(1,2)
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
CLK0
CLK1
CLK0
CLK1
Q0 to Q3
Disabled; LOW
Disabled; LOW
Enabled
Enabled
Outputs
xQ0 to xQ3
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
NOTES:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below.
2. In active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table.
Disabled
CLK0, CLK1
Enabled
≈
≈
≈
CLK_EN Timing Diagram
CLK_EN
xQ0, xQ1, xQ2, xQ3
Q0, Q1, Q2, Q3
CLOCK INPUT FUNCTION TABLE
(1)
Inputs
CLK0 or CLK1
0
1
NOTE:
1. H = HIGH
L = LOW
Outputs
Q0 to Q3
L
H
xQ0 to xQ3
H
L
3
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS - COMMERCIAL
Symbol
V
DD
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Min.
3.135
—
Typ.
3.3
—
Max.
3.465
50
Unit
V
mA
DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL - COMMERCIAL
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input Voltage HIGH
Input Voltage LOW
Input Current HIGH
Input Current LOW
CLK0, CLK1
CLK_EN, CLK_SEL
CLK0, CLK1, CLK_SEL
CLK_EN
CLK0, CLK1, CLK_SEL
CLK_EN
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-5
-150
Test Conditions
Min.
2
-0.3
-0.3
Typ.
Max.
V
DD
+ 0.3
1.3
0.8
150
5
µA
µA
Unit
V
V
DC ELECTRICAL CHARACTERISTICS, LVPECL - COMMERCIAL
Symbol
V
OH
V
OL
V
SWING
Parameter
Output Voltage HIGH
(1)
Output Voltage LOW
(1)
Peak-to-Peak Output Voltage Swing
Test Conditions
Min.
V
DD
- 1.4
V
DD
- 2
0.6
Typ.
Max.
V
DD
- 1
V
DD
- 1.7
0.85
Unit
V
V
V
NOTE:
1. Outputs terminated with 50Ω to V
DD
- 2V.
AC ELECTRICAL CHARACTERISTICS - COMMERCIAL
All parameters measured at 266MHz unless noted otherwise;
Cycle-to-cycle jitter on input = jitter on output; the part does not add jitter
Symbol
F
MAX
t
PD
t
SK
(
O
)
t
SK
(
PP
)
t
R
t
F
odc
Parameter
Output Frequency
Propagation Delay
(1)
Output Skew
(2,4)
Part-to-Part Skew
(3,4)
Output Rise Time
Output Fall Time
Output Duty Cycle
20 - 80% @ 50MHz
20 - 80% @ 50MHz
300
300
48
50
f
≤
266MHz
1
11
Test Conditions
Min.
Typ.
Max.
266
1.9
30
150
700
700
52
Unit
MHz
ns
ps
ps
ps
ps
%
NOTES:
1. Measured from the V
DD
/2 of the input to the differential output crossingpoint.
2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints
3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each
device, the outputs are measured at the differential crosspoints.
4. This parameter is defined in accordance with JEDEC Standard 65.
4
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS - INDUSTRIAL
Symbol
V
DD
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Min.
3.135
—
Typ.
3.3
—
Max.
3.465
55
Unit
V
mA
DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL - INDUSTRIAL
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input Voltage HIGH
Input Voltage LOW
Input Current HIGH
Input Current LOW
CLK0, CLK1
CLK_EN, CLK_SEL
CLK0, CLK1, CLK_SEL
CLK_EN
CLK0, CLK1, CLK_SEL
CLK_EN
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-5
-150
Test Conditions
Min.
2
-0.3
-0.3
Typ.
Max.
V
DD
+ 0.3
1.3
0.8
150
5
µA
µA
Unit
V
V
DC ELECTRICAL CHARACTERISTICS, LVPECL - INDUSTRIAL
Symbol
V
OH
V
OL
V
SWING
Parameter
Output Voltage HIGH
(1)
Output Voltage LOW
(1)
Peak-to-Peak Output Voltage Swing
Test Conditions
Min.
V
DD
- 1.4
V
DD
- 2
0.6
Typ.
Max.
V
DD
- 1
V
DD
- 1.7
0.85
Unit
V
V
V
NOTE:
1. Outputs terminated with 50Ω to V
DD
- 2V.
AC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
All parameters measured at 266MHz unless noted otherwise;
Cycle-to-cycle jitter on input = jitter on output; the part does not add jitter
Symbol
F
MAX
t
PD
t
SK
(
O
)
t
SK
(
PP
)
t
R
t
F
odc
Parameter
Output Frequency
Propagation Delay
(1)
Output Skew
(2,4)
Part-to-Part Skew
(3,4)
Output Rise Time
Output Fall Time
Output Duty Cycle
20 - 80% @ 50MHz
20 - 80% @ 50MHz
300
300
48
50
f
≤
266MHz
1
Test Conditions
Min.
Typ.
Max.
266
1.9
30
200
700
700
52
Unit
MHz
ns
ps
ps
ps
ps
%
NOTES:
1. Measured from the V
DD
/2 of the input to the differential output crossingpoint.
2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints
3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each
device, the outputs are measured at the differential crosspoints.
4. This parameter is defined in accordance with JEDEC Standard 65.
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stm32/stm8
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