8:1 Differential-to-LVDS Clock Multiplexer
ICS854S058I
DATASHEET
General Description
The ICS854S058I is an 8:1 Differential-to-LVDS Clock Multiplexer
which can operate up to 2.5GHz. The ICS854S058I has 8
selectable differential clock inputs. The PCLK, nPCLK input pairs
can accept LVPECL, LVDS, SSTL or CML levels. The fully
differential architecture and low propagation delay make it ideal for
use in clock distribution circuits. The select pins have internal
pulldown resistors. The SEL2 pin is the most significant bit and the
binary number applied to the select pins will select the same
numbered data input (i.e., 000 selects PCLK0, nPCLK0).
Features
•
•
•
•
•
•
•
•
•
•
•
•
High speed 8:1 differential multiplexer
One differential LVDS output pair
Eight selectable differential PCLK, nPCLK input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, SSTL, CML
Maximum output frequency: 2.5GHz
Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx input
Additive phase jitter, RMS: 0.065ps (typical)
Part-to-part skew: 300ps (maximum)
Propagation delay: 600ps (maximum)
Supply voltage range: 3.135V to 3.465V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packaging
Block Diagram
PCLK0
Pulldown
nPCLK0
Pullup/Pulldown
PCLK1
Pulldown
nPCLK1
Pullup/Pulldown
PCLK2
Pulldown
nPCLK2
Pullup/Pulldown
PCLK3
Pulldown
nPCLK3
Pullup/Pulldown
PCLK4
Pulldown
nPCLK4
Pullup/Pulldown
PCLK5
Pulldown
nPCLK5
Pullup/Pulldown
PCLK6
Pulldown
nPCLK6
Pullup/Pulldown
PCLK7
Pulldown
nPCLK7
Pullup/Pulldown
000
(default)
Pin Assignment
PCLK0
nPCLK0
PCLK1
nPCLK1
V
DD
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PCLK7
nPCLK7
PCLK6
nPCLK6
V
DD
Q
nQ
GND
PCLK5
nPCLK5
PCLK4
nPCLK4
001
010
011
Q
nQ
100
ICS854S058I
24-Lead TSSOP, 173-MIL
7.8mm x 4.4mm x 0.925mm package body
G Package
Top View
101
110
111
SEL2
Pulldown
SEL1
Pulldown
SEL0
Pulldown
ICS854S058AGI REVISION A OCTOBER 29, 2012
1
©2012 Integrated Device Technology, Inc.
ICS854S058I Datasheet
8:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5, 20
6, 7, 8
9
10
11
12
13
14
15
16
17
18, 19
21
22
23
24
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
V
DD
SEL0,
SEL1,
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
nPCLK4
PCLK4
nPCLK5
PCLK5
GND
nQ, Q
nPCLK6
PCLK6
nPCLK7
PCLK7
Input
Input
Input
Input
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power
Output
Input
Input
Input
Input
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Type
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
Positive supply pins.
Clock select input pins. LVCMOS/LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
Non-inverting differential LVPECL clock input.
Power supply ground.
Differential output pair. LVDS interface levels.
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
Non-inverting differential LVPECL clock input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
VDD
/2
Parameter
Input Capacitance
Pulldown Resistor
RPullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
75
50
Maximum
Units
pF
k
k
ICS854S058AGI REVISION A OCTOBER 29, 2012
2
©2012 Integrated Device Technology, Inc.
ICS854S058I Datasheet
8:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Table 3. Clock Input Function Table
Inputs
SEL2
0 (default)
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Q
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
Outputs
nQ
nPCLK0
nPCLK1
nPCLK2
nPCLK3
nPCLK4
nPCLK5
nPCLK6
nPCLK7
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
85.1°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
66
Units
V
mA
ICS854S058AGI REVISION A OCTOBER 29, 2012
3
©2012 Integrated Device Technology, Inc.
ICS854S058I Datasheet
8:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SEL[0:2]
SEL[0:2]
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-10
Test Conditions
Minimum
2.2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
µA
Table 4C. LVPECL Differential DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
PCLK[0:7],
nPCLK[0:7]
PCLK[0:7]
Input Low Current
nPCLK[0:7]
Peak-to-Peak Voltage;
NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-10
-150
0.15
GND + 1.2
1.2
V
DD
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Table 4D. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.125
Test Conditions
Minimum
247
Typical
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
ICS854S058AGI REVISION A OCTOBER 29, 2012
4
©2012 Integrated Device Technology, Inc.
ICS854S058I Datasheet
8:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Table 5. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
OUT
t
PD
tjit(Ø)
Parameter
Output Frequency
Propagation Delay;
NOTE 1
Buffer Additive Phase Jitter,
RMS; Refer to Additive Phase
Jitter Section
Part-to-Part Skew;
NOTE 2, 3
Input Skew
Output Rise/Fall Time
MUX Isolation;
NOTE 4
20% to 80%
155.52MHz, V
PP
= 400mV
75
85
155.52MHz, Integration Range:
12kHz – 20MHz
300
Test Conditions
Minimum
Typical
Maximum
2.5
600
Units
GHz
ps
0.065
ps
tsk(pp)
tsk(i)
t
R
/ t
F
MUX
ISOLATION
300
50
250
ps
ps
ps
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
All parameters measured
1.0GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Q/nQ output measured differentially. See
Parameter Measurement Information
for MUX Isolation diagram.
ICS854S058AGI REVISION A OCTOBER 29, 2012
5
©2012 Integrated Device Technology, Inc.
京公网安备 11010802033920号
EEWORLD
