a
FEATURES
Pin Compatible to the AD6622
18-Bit Parallel Digital IF Output
Real or Interleaved Complex
18-Bit Bidirectional Parallel Digital IF Input/Output
Allows Cascade of Chips for Additional Channels
Clipped or Wrapped Over Range
Two’s Complement or Offset Binary Output
Four Independent Digital Transmitters in Single Package
RAM Coefficient Filter (RCF)
Programmable IF and Modulation for Each Channel
Programmable Interpolating RAM Coefficient Filter
p/4-DQPSK Differential Phase Encoder
3p/8-PSK Linear Encoder
8-PSK Linear Encoder
Programmable GMSK Look-Up Table
Programmable QPSK Look-Up Table
All-Pass Phase Equalizer
Programmable Fine Scaler
Programmable Power Ramp Unit
High Speed CIC Interpolating Filter
4-Channel, 104 MSPS Digital
Transmit Signal Processor (TSP)
AD6623
Digital Resampling for Noninteger Interpolation Rates
NCO Frequency Translation
Spurious Performance Better than –100 dBc
Separate 3-Wire Serial Data Input for Each Channel
Bidirectional Serial Clocks and Frames
Microprocessor Control
2.5 V CMOS Core, 3.3 V Outputs, 5 V Inputs
JTAG Boundary Scan
APPLICATIONS
Cellular/PCS Base Stations
Micro/Pico Cell Base Stations
Wireless Local Loop Base Stations
Multicarrier, Multimode Digital Transmit
GSM, EDGE, IS136, PHS, IS95, TDS CDMA, UMTS,
CDMA2000
Phased Array Beam Forming Antennas
Software Defined Radio
Tuning Resolution Better than 0.025 Hz
Real or Complex Outputs
FUNCTIONAL BLOCK DIAGRAM
NCO = NUMERICALLY CONTROLLED
OSCILLATOR/TUNER
SDINA
DATA
SDFIA
SDFOA
SCLKA
SDINB
SDFIB
SDFOB
SCLKB
SUMMATION
SDINC
DATA
SDFIC
SDFOC
SCLKC
SDIND
SDFID
SDFOD
SCLKD
SP
ORT
I
RAM
COEFFICIENT Q
FILTER
SCALER I
AND
Q
POWER
RAMP
I
CIC5
FILTER
Q
RCIC2
FILTER
I
Q
NCO
OUT
[17:0]
SP
ORT
I
RAM
COEFFICIENT Q
FILTER
SCALER I
AND
Q
POWER
RAMP
I
CIC5
FILTER
Q
RCIC2
FILTER
I
Q
NCO
CHAN C
SP
ORT
DATA
I
RAM
COEFFICIENT Q
FILTER
SCALER I
AND
Q
POWER
RAMP
I
CIC5
FILTER
Q
RCIC2
FILTER
I
Q
NCO
SP
ORT
I
RAM
COEFFICIENT Q
FILTER
SCALER I
AND
Q
POWER
RAMP
I
CIC5
FILTER
Q
RCIC2
FILTER
I
Q
NCO
CHAN A
QIN
IN
[17–0]
CHAN B
SYNC
4
OEN
DATA
CHAN D
QOUT
JTAG
MICROPORT
TDL
TDO TMS TCK
TRST
D[7:0]
DS
DTACK
RW
MODE A[2:0]
CS
CLK
RESET
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD6623
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . 4
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 4
LOGIC INPUTS (5 V TOLERANT) . . . . . . . . . . . . . . . . . . . . . . . . . 4
LOGIC OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
IDD SUPPLY CURRENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
GENERAL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5
MICROPROCESSOR PORT TIMING CHARACTERISTICS . . . . . . . . 6
MICROPROCESSOR PORT, MODE INM (MODE = 0) . . . . . . . . . 6
MICROPROCESSOR PORT, MOTOROLA (MODE = 1) . . . . . . . . 6
TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . 10
THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PIN CONFIGURATION – 128-Lead MQFP . . . . . . . . . . . . . . . . . . . . 11
128 PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 12
PIN CONFIGURATION – 196-Lead BGA . . . . . . . . . . . . . . . . . . . . . . 13
196 PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 14
POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
JTAG AND BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SERIAL DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial Master Mode (SCS = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial Slave Mode (SCS = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Self-Framing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
External Framing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial Port Cascade Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PROGRAMMABLE RAM COEFFICIENT FILTER (RCF) . . . . . . . . . 16
OVERVIEW OF THE RCF BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . 16
INTERPOLATING FIR FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RCF CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PSK MODULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
/4-DQSPK MODULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8-PSK MODULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 /8-8-PSK MODULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MSK Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
GMSK Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
QPSK Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PHASE EQUALIZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SCALE AND RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FINE SCALING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RCF POWER RAMPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CASCADED INTERGRATOR COMB (CIC)
INTERPOLATING FILTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CIC Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CIC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
rCIC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
NUMERICALLY CONTROLLED
OSCILLATOR/TUNER (NCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Phase Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Amplitude Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
NCO Frequency Update and Phase Offset Update
Hold-Off Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
NCO Control Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SUMMATION BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Start with No Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Start with Soft Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Start with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Hop with Soft Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Hop with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Beam with Soft Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Beam with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
JTAG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SCALING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Multicarrier Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Single Carrier Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MICROPORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MicroPort Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
EXTERNAL MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Intel Nonmultiplexed Mode (INM) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Motorola Nonmultiplexed Mode (MNM) . . . . . . . . . . . . . . . . . . . . . 30
External Address 7 Upper Address Register (UAR) . . . . . . . . . . . . . . 30
External Address 6 Lower Address Register (LAR) . . . . . . . . . . . . . . 30
External Address 5 Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
External Address 4 Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
External Address 3:0 (Data Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
INTERNAL CONTROL REGISTERS AND ON-CHIP RAM . . . . . . . . . 31
AD6623 and AD6622 Compatibility
Common Function Registers (not associated
with a particular channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Channel Function Registers (0x1XX = Ch. A,
0x2XX = Ch. B, 0x3XX = Ch. C, 0x4XX = Ch. D) . . . . . . . . . . . 31
(0x000) Summation Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . 33
(0x001) Sync Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
(0x002) BIST Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
(0x003) BIST Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Channel Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn00) Start Update Hold-Off Counter . . . . . . . . . . . . . . . . . . . . . . 34
(0xn01) NCO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn02) NCO Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn03) NCO Frequency Update Hold-Off Counter . . . . . . . . . . . . . 34
(0xn04) NCO Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn05) NCO Phase Offset Update Hold-Off Counter . . . . . . . . . . . . 34
(0xn06) CIC Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn07) CIC2 Decimation – 1 (M
CIC2
– 1) . . . . . . . . . . . . . . . . . . . . . 34
(0xn08) CIC2 Interpolation – 1 (L
CIC2
– 1) . . . . . . . . . . . . . . . . . . . . 34
(0xn09) CIC5 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn0A) Number of RCF Coefficients – 1 . . . . . . . . . . . . . . . . . . . . . 34
(0xn0B) RCF Coefficient Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn0C) Channel Mode Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn0D) Channel Mode Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn0E) Fine Scale Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn0F) RCF Time Slot Hold-Off Counter . . . . . . . . . . . . . . . . . . . . 35
(0xn10–0xn11) RCF Phase Equalizer Coefficients . . . . . . . . . . . . . . . 35
(0xn12–0xn15) FIR-PSK Magnitudes . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn16) Serial Port Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn17) Power Ramp Length 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn18) Power Ramp Length 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn19) Power Ramp Rest Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn20–0xn1F) Unused . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn20–0xn3F) Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn40–0xn17F) Power Ramp Coefficient Memory . . . . . . . . . . . . . . 35
Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Write Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
USING THE AD6623 TO PROCESS UMTS CARRIERS . . . . . . . . 36
DIGITAL-TO-ANALOG CONVERTER (DAC) SELECTION . . . . . . . 36
MULTIPLE TSP OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Determining the Number of TSPs to Use . . . . . . . . . . . . . . . . . . . . 36
Programming Mulitple TSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Driving Multiple TSP Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . 37
THERMAL MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PACKAGE OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 39
–2–
REV. 0
AD6623
PRODUCT DESCRIPTION
The AD6623 is a 4-channel Transmit Signal Processor (TSP)
that creates high bandwidth data for Transmit Digital-to-Analog
Converters (TxDACs) from baseband data provided by a Digital
Signal Processor (DSP). Modern TxDACs have achieved suffi-
ciently high sampling rates, analog bandwidth, and dynamic range
to create the first Intermediate Frequency (IF) directly. The
AD6623 synthesizes multicarrier and multistandard digital signals
to drive these TxDACs. The RAM-based architecture allows easy
reconfiguration for multimode applications. Modulation, pulse-
shaping and anti-imaging filters, static equalization, and tuning
functions are combined in a single, cost-effective device. Digital
IF signal processing provides repeatable manufacturing, higher
accuracy, and more flexibility than comparable high dynamic
range analog designs.
The AD6623 has four identical digital TSPs complete with synchro-
nization circuitry and cascadable wideband channel summation.
AD6623 is pin compatible to AD6622 and can operate in AD6622-
compatible control register mode.
The AD6623 utilizes a 3.3 V I/O power supply and a 2.5 V core
power supply. All I/O pins are 5 V tolerant. All control registers
and coefficient values are programmed through a generic micro-
processor interface. Intel and Motorola microprocessor bus modes
are supported. All inputs and outputs are LVCMOS compatible.
FUNCTIONAL OVERVIEW
INOUT[17:0] can alternatively be masked off by software to
allow preceding AD6623’s outputs to be ignored.
Each channel accepts input data from independent serial ports
that may be connected directly to the serial port of Digital Signal
Processor (DSP) chips.
The RCF implements any one of the following functions:
Interpolating Finite Impulse Response (FIR) filter, /4-DQPSK
modulator, 8-PSK modulator, or 3 /8-8-PSK modulator, GMSK
modulator, and QPSK modulator. Each AD6623 channel can
be dynamically switched between the GMSK modulation mode
and the 3 /8-8-PSK modulation mode in order to support the
GSM/EDGE standard. The RCF also implements an Allpass
Phase Equalizer (APE) which meets the requirements of IS-95-A/B
standard (CDMA transmission).
The programmable Scale and Power Ramp block allows power
ramping on a time-slot basis as specified for some air-interface
standards (e.g., GSM, EDGE). A fine scaling unit at the pro-
grammable FIR filter output allows an easy signal amplitude
level adjustment on time slot basis.
The CIC5 provides integer rate interpolation from 1 to 32 and
coarse anti-image filtering. The rCIC2 provides fractional rate
interpolation from 1 to 4096 in steps of 1/512. The wide range
of interpolation factors in each CIC filter stage and a highly
flexible resampler incorporated into rCIC2 makes the AD6623
useful for creating both narrowband and wideband carriers in a
high-speed sample stream.
The high resolution 32-bit NCO allows flexibility in frequency
planning and supports both digital and analog air interface stan-
dards. The high speed NCO tunes the interpolated complex signal
from the rCIC2 to an IF channel. The result may be real or com-
plex. Multicarrier phase synchronization pins and phase offset
registers allow intelligent management of the relative phase of
independent RF channels. This capability supports the require-
ments for phased array antenna architectures and management
of the wideband peak/power ratio to minimize clipping at the DAC.
The wideband Output Ports can deliver real or complex data.
Complex words are interleaved into real (I) and imaginary (Q)
parts at half the master clock rate.
Each TSP has five cascaded signal processing elements: a pro-
grammable interpolating RAM Coefficient Filter (RCF), a
programmable Scale and Power Ramp, a programmable fifth order
Cascaded Integrator Comb (CIC5) interpolating filter, a flexible
second order Resampling Cascaded Integrator Comb filter (rCIC2),
and a Numerically Controlled Oscillator/Tuner (NCO).
The outputs of the four TSPs are summed and scaled on-chip.
In multicarrier wideband transmitters, a bidirectional bus allows
the Parallel (wideband) IF Input/Output to drive a second DAC.
In this operational mode two AD6623 channels drive one DAC
and the other two AD6623 channels drive a second DAC. Mul-
tiple AD6623s may be combined by driving the INOUT[17:0] of
the succeeding with the OUT[17:0] of the preceding chip. The
REV. 0
–3–
京公网安备 11010802033920号
EEWORLD
