ACT–F128K32 High Speed
4 Megabit FLASH Multichip Module
CIRCUIT TECHNOLOGY
Features
■
4 Low Power 128K x 8 FLASH Die in One MCM
www.aeroflex.com
Package
■
Organized as 128K x 32
●
User Configurable to 256K x 16 or 512K x 8
●
Upgradable to 512K x 32 in same Package Style
■
Access Times of 60, 70, 90, 120 and 150ns
■
+5V Programing, 5V ±10% Supply
■
100,000 Erase/Program Cycles Typical, 0°C to +70°C
■
Low Standby Current
■
TTL Compatible Inputs and CMOS Outputs
■
Embedded Erase and Program Algorithms
■
Page Program Operation and Internal Program
Control Time
■
Commercial, Industrial and Military Temperature
Ranges
■
MIL-PRF-38534 Compliant MCMs Available
■
Industry Standard Pinouts
■
Packaging – Hermetic Ceramic
Lead, .88" x .88" x .160" Single-Cavity Small
Outline gull wing, Aeroflex code# "F5"
(Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
●
66 Pin, 1.08" x 1.08" x .160" PGA Type, No
Shoulder, Aeroflex code# "P3"
●
66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
■
Sector Architecture (Each Die)
●
8 Equal size sectors of 64K bytes each
●
Any Combination of Sectors can be erased with
one command sequence
●
Supports Full Chip Erase
■
DESC SMD# 5962–94716 Released (P3,P7,F5)
●
68
Block Diagram – PGA Type Package (P3,P7) & CQFP (F5)
WE
1
CE
1
WE
2
CE
2
WE
3
CE
3
WE
4
CE
4
OE
A
0
–A
16
General Description
The ACT–F128K32 is a high
speed, 4 megabit CMOS flash
multichip
module
(MCM)
designed for full temperature
range military, space, or high
reliability applications.
The MCM can be organized
as a 128K x 32 bits, 256K x 16
bits or 512K x 8 bits device and
is input TTL and output CMOS
compatible.
The
command
register is written by bringing
WE to a logic low level (V
IL
),
while CE is low and OE is at
logic high level (V
IH
)
. Reading is
accomplished by chip Enable
(CE) and Output Enable (OE)
being logically active, see
Figure 9. Access time grades of
60ns, 70ns, 90ns, 120ns and
150ns maximum are standard.
The
ACT–F128K32
is
packaged in a hermetically
128Kx8
8
I/O
0-7
128Kx8
8
I/O
8-15
128Kx8
8
I/O
16-23
128Kx8
8
I/O
24-31
Pin Description
I/O
0-31
Data I/O
A
0–16
Address Inputs
WE
1-4
Write Enables
CE
1-4
OE
V
CC
GND
NC
Chip Enables
Output Enable
Power Supply
Ground
Not Connected
eroflex Circuit Technology - Advanced Multichip Modules © SCD1667 REV C 10/28/02
General Description, Cont’d
,
sealed co-fired ceramic 66 pin, 1.08" sq
PGA or a 68 lead, .88" sq Ceramic Gull
Wing CQFP package for operation over the
temperature range of -55°C to +125°C and
military environment.
Each flash memory die is organized as
128KX8 bits and is designed to be
programmed in-system with the standard
system 5.0V Vcc supply. A 12.0V V
PP
is
not required for write or erase operations.
The MCM can also be reprogrammed with
standard EPROM programmers (with the
proper socket).
The standard ACT-F128K32 offers
access times between 60ns and 150ns,
allowing
operation
of
high-speed
microprocessors without wait states. To
eliminate bus contention, the device has
separate chip enable (CE) and write enable
(WE). The ACT-F128K32 is command set
compatible with JEDEC standard 1 Mbit
EEPROMs. Commands are written to the
command
register
using
standard
microprocessor write timings. Register
contents serve as input to an internal
state-machine which controls the erase and
programming circuitry. Write cycles also
internally latch addresses and data needed
for the programming and erase operations.
Reading data out of the device is similar
to reading from 12.0V Flash or EPROM
devices. The ACT-F128K32 is programmed
by executing the program command
sequence. This will invoke the Embedded
Program Algorithm which is an internal
algorithm that automatically times the
program pulse widths and verifies proper
cell margin. Typically, each sector can be
programmed and verified in less than 0.3
second. Erase is accomplished by
executing the erase command sequence.
This will invoke the Embedded Erase
Algorithm which is an internal algorithm
that automatically preprograms the array, (if
it is not already programmed before)
executing the erase operation. During
erase, the device automatically times the
erase pulse widths and verifies proper cell
margin.
Each die in the module or any individual
sector of the die is typically erased and
verified in 1.3 seconds (if already
completely preprogrammed).
Each die also features a sector erase
architecture. The sector mode allows for
16K byte blocks of memory to be erased
and reprogrammed without affecting other
blocks. The ACT-F128K32 is erased when
shipped from the factory.
The device features single 5.0V power
supply operation for both read and write
functions.
lnternally
generated
and
regulated voltages are provided for the
program and erase operations. A low V
CC
detector
automatically inhibits
write
operations on the loss of power. The end of
program or erase is detected by Data
Polling of D7 or by the Toggle Bit feature on
D6. Once the end of a program or erase
cycle has been completed,-+ the device
internally resets to the read mode.
All bits of each die, or all bits within a
sector of a die, are erased via
Fowler-Nordhiem tunneling. Bytes are
programmed one byte at a time by hot
electron injection.
DESC Standard Military Drawing (SMD)
numbers are released.
A
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2
SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700
Absolute Maximum Ratings
Parameter
Case Operating Temperature
Storage Temperature Range
Supply Voltage Range
Signal Voltage Range (Any Pin Except A9) Note 1
Maximum Lead Temperature (10 seconds)
Data Retention
Endurance (Write/Erase cycles)
A9 Voltage for sector protect, Note 2
V
ID
Symbol
T
C
T
STG
V
CC
V
G
Range
-55 to +125
-65 to +150
-2.0 to +7.0
-2.0 to +7.0
300
10
100,000 Minimum
-2.0 to +14.0
V
Units
°C
°C
V
V
°C
Years
Note 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot V
SS
to -2.0v for periods of up
to 20ns. Maximum DC voltage on input and I/O pins is V
CC
+ 0.5V. During voltage transitions, inputs and I/O pins may overshoot to
V
CC
+ 2.0V for periods up to 20 ns.
Note 2. Minimum DC input voltage on A9 is -0.5V. During voltage transitions, A9 may undershoot V
SS
to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns.
Normal Operating Conditions
Symbol
V
CC
V
IH
V
IL
T
C
V
ID
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature (Military)
A9 Voltage for sector protect
Minimum
+4.5
+2.0
-0.5
-55
11.5
Maximum
+5.5
V
CC
+ 0.5
+0.8
+125
12.5
Units
V
V
V
°C
V
A
Capacitance
(V
IN
= 0V, f = 1MHz, T
C
= 25°C)
Symbol
C
AD
C
OE
C
WE
Parameter
A
0
– A
16
Capacitance
OE Capacitance
Write Enable Capacitance
CQFP(F5) Package
PGA(P3,P7) Package
C
CE
C
I
/
O
Chip Enable Capacitance
I/O0 – I/O31 Capacitance
20
20
20
20
pF
pF
pF
pF
Maximum
50
50
Units
pF
pF
Parameters Guaranteed but not tested
DC Characteristics – CMOS Compatible
(Vcc = 5.0V, Vss = 0V, T
C
= -55°C to +125°C, unless otherwise indicated)
Parameter
Input Leakage Current
Output Leakage Current
Active Operating Supply Current for Read (1)
Active Operating Supply Current for Program or Erase(2)
Standby Supply Current
Static Supply Current (4)
Output Low Voltage
Output High Voltage
Output High Voltage (4)
Low Power Supply Lock-Out Voltage (4)
Sym
I
LI
Conditions
V
CC
= 5.5V, Vi
N
= GND to V
CC
CE = V
IL
,
OE = V
IH
, f = 5MHz
CE = V
IL
,
OE = V
IH
V
CC
= 5.5V, CE = V
IH
, f = 5MHz
V
CC
= 5.5V, CE = V
IH
I
OL
= +8.0 mA, V
CC
= 4.5V
I
OH
= –2.5 mA, V
CC
= 4.5V
I
OH
= –100 µA, V
CC
= 4.5V
0.85 x V
CC
V
CC
– 0.4
3.2
Speeds 60, 70, 90, 120 & 150ns
Minimum
Maximum
10
10
140
200
6.5
0.6
0.45
Units
µA
µA
mA
mA
mA
mA
V
V
V
V
I
LOX
32 V
CC
= 5.5V, Vi
N
= GND to V
CC
I
CC
1
I
CC
2
I
CC
3
I
CC
4
V
OL
V
OH
1
V
OH
2
V
LKO
Note 1. The Icc current listed includes both the DC operating current and the frequency dependent component (At 5 MHz). The frequency
component typically is less than 2 mA/MHz, with OE at V
IN
.
Note 2. Icc active while Embedded Algorithm (Program or Erase) is in progress.
Note 3. DC Test conditions: V
IL
= 0.3V, V
IH
= V
CC
- 0.3V, unless otherwise indicated
Note 4. Parameter Guaranteed but not tested.
Aeroflex Circuit Technology
3
SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700
Characteristics – Read Only Operations
(Vcc = 5.0V, Vss = 0V, T
C
= -55°C to +125°C)
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable to Output Valid
Chip Enable to Output High Z (1)
Output Enable High to Output High Z (1)
Output Hold from Address, CE or OE Change, whichever is first
Note 1. Guaranteed by design, but not tested
Symbol
JEDEC Stand’d
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
t
RC
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
0
–60
60
60
60
30
20
20
0
–70
70
70
70
35
20
20
0
–90
90
90
90
40
25
25
0
–120
Min Max
120
120
120
50
30
30
0
–150
Min Max
150
150
150
55
35
35
Min Max Min Max Min Max
Units
ns
ns
ns
ns
ns
ns
ns
AC Characteristics – Write/Erase/Program Operations, WE Controlled
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Parameter
Write Cycle Time
Chip Enable Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Enable Hold Time (1)
Write Enable Pulse Width High
Duration of Byte Programming Operation
Sector Erase Time
Chip Erase Time
Read Recovery Time before Write (1)
Vcc Setup Time (1)
Chip Programming Time
Output Enable Setup Time (1)
Output Enable Hold Time (1)
Note 1. Guaranteed by design, but not tested
t
OES
t
OEH
0
10
Symbol
t
AVAC
t
ELWL
t
WLWH
t
AVWL
t
DVWH
t
WHDX
t
WLAX
t
WHEH
t
WHWL
t
WHWH
1
t
WHWH
2
t
WHWH
3
t
WC
t
CE
t
WP
t
AS
t
DS
t
DH
t
AH
t
CH
t
WPH
–60
60
0
30
0
30
0
45
0
20
60
120
0
t
VCE
50
12.5
0
10
0
50
12.5
0
10
–70
70
0
35
0
30
0
45
0
20
60
120
0
50
12.5
0
10
–90
90
0
45
0
45
0
45
0
20
60
120
0
50
12.5
0
10
–120
Min Max
120
0
50
0
50
0
50
0
20
14
TYP
60
120
0
50
12.5
–150
Min Max
150
0
50
0
50
0
50
0
20
14
TYP
60
120
JEDEC Stand’d Min Max Min Max Min Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Sec
Sec
µs
µs
Sec
ns
ns
A
14 TYP 14 TYP 14 TYP
t
GHWL
AC Characteristics – Write/Erase/Program Operations, CE Controlled
(Vcc = 5.0V, Vss = 0V, T
C
= -55°C to +125°C)
Parameter
Write Cycle Time
Write Enable Setup Time
Chip Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Hold Time (1)
Write Select Pulse Width High
Duration of Byte Programming
Sector Erase Time
Chip Erase Time
Read Recovery Time (1)
Chip Programming Time
Note 1. Guaranteed by design, but not tested
Symbol
t
AVAC
t
WLE
L
t
ELEH
t
AVEL
t
DVEH
t
EHDX
t
ELAX
t
EHWH
t
EHEL
t
WHWH
1
t
WHWH
2
t
WHWH
3
t
WC
t
WS
t
CP
t
AS
t
DS
t
DH
t
AH
t
WH
t
CPH
–60
60
0
35
0
30
0
45
0
20
60
120
0
12.5
0
12.5
–70
70
0
35
0
30
0
45
0
20
60
120
0
12.5
–90
90
0
45
0
45
0
45
0
20
60
120
0
12.5
–120
Min Max
120
0
50
0
50
0
50
0
20
14
TYP
60
120
0
12.5
–150
Min Max
150
0
55
0
55
0
55
0
20
14
TYP
60
120
JEDEC Stand’d Min Max Min Max Min Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Sec
Sec
ns
Sec
14 TYP 14 TYP 14 TYP
t
GHEL
Aeroflex Circuit Technology
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SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700
Device Operation
The ACT-F128K32 MCM is composed of four, one
megabit flash EEPROMs. The following description is for
the individual flash EEPROM device, is applicable to
each of the four memory chips inside the MCM. Chip 1 is
distinguished by CE
1
and I/O
1-7
, Chip 2 by CE
2
and
I/0
8-15
, Chip 3 by CE
3
and I/0
16-23
, and Chip 4 by CE
4
and
I/0
24-31
.
Programming of the ACT-F128K32 is accomplished by
executing the program command sequence.
The
program algorithm, which is an internal algorithm,
automatically times the program pulse widths and verifies
proper cell status. Sectors can be programed and
verified in less than 0.3 second. Erase is accomplished
by executing the erase command sequence. The erase
algorithm, which is internal, automatically preprograms
the array if it is not already programed before executing
the erase operation.
During erase, the device
automatically times the erase pulse widths and verifies
proper cell status. The entire memory is typically erased
and verified in 3 seconds (if pre-programmed). The
sector mode allows for 16K byte blocks of memory to be
erased and reprogrammed without affecting other blocks.
current consumed is typically less than 400 µA; and a
TTL standby mode (CE is held V
IH
) is approximately 1
mA. In the standby mode the outputs are in a high
impedance state, independent of the OE input.
If the device is deselected during erasure or
programming, the device will draw active current until the
operation is completed.
WRITE
Device erasure and programming are accomplished via
the command register. The contents of the register serve
as input to the internal state machine. The state machine
outputs dictate the function of the device.
The command register itself does not occupy an
addressable memory location. The register is a latch
used to store the command, along with address and data
information needed to execute the command. The
command register is written by bringing WE to a logic low
level (V
IL
), while CE is low and OE is at V
IH
. Addresses
are latched on the falling edge of WE or CE, whichever
happens later. Data is latched on the rising edge of the
WE or CE whichever occurs first.
Standard
microprocessor write timings are used. Refer to AC
Program Characteristics and Waveforms, Figures 3,
8 and 13.
A
Bus Operation
READ
The ACT-F128K32 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output-Enable (OE)
is the output control and should be used to gate data to
the output pins of the chip selected. Figure 7 illustrates
AC read timing waveforms.
Command Definitions
Device operations are selected by writing specific
address and data sequences into the command register.
Table 3 defines these register command sequences.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for reads
until the command register contents are altered.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data.
The device will automatically
power-up in the read/reset state. In this case, a command
sequence is not required to read data.
Standard
Microprocessor read cycles will retrieve array data. This
Table 2 – Sector Addresses Table
OUTPUT DISABLE
With Output-Enable at a logic high level (V
IH
), output from
the device is disabled. Output pins are placed in a high
impedance state.
STANDBY MODE
The ACT-F128K32 has two standby modes, a CMOS
standby mode (CE input held at Vcc + 0.5V), where the
Table 1 – Bus Operations
Operation
READ
STANDBY
OUTPUT DISABLE
WRITE
ENABLE SECTOR
PROTECT
VERIFY SECTOR
PROTECT
CE OE WE A0 A1 A9
L
H
L
L
L
L
L
X
H
H
V
ID
L
H
X
H
L
L
H
A
0
A
1
A
9
X
X
X
X
X
X
I/O
DOUT
HIGH Z
HIGH Z
D
IN
X
Code
A16 A15
SA0
SA1
SA2
SA3
SA4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
A14
0
1
0
1
0
1
0
1
Address Range
00000h – 03FFFh
04000h – 07FFFh
08000h – 0BFFFh
0C000h – 0FFFFh
10000h – 13FFFh
14000h – 17FFFh
18000h – 1BFFFh
1C000h – 1FFFFh
A
0
A
1
A
9
X
L
X
H
V
ID
V
ID
SA5
SA6
SA7
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SCD1667 REV C 10/28/02 Plainview NY (516) 694-6700
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