Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5634M
Rev. 4, 12/2009
MPC5634M
144 LQFP
20 mm x 20 mm
208 MAPBGA
17 mm x 17 mm
MPC5634M Microcontroller
Data Sheet
• Operating Parameters
– Fully static operation, 0 MHz - 80 MHz (plus 2%
frequency modulation - 82 MHz)
– -40
°C
to 150
°C
junction temperature operating range
– Low power design
– Less than 400 mW power dissipation (nominal)
– Designed for dynamic power management of core
and peripherals
– Software controlled clock gating of peripherals
– Low power stop mode, with all clocks stopped
– Fabricated in 90 nm process
– 1.2 V internal logic
• High performance e200z335 core processor
• Advanced microcontroller bus architecture (AMBA)
crossbar switch (XBAR)
• Enhanced direct memory access (eDMA) controller
• Interrupt controller (INTC)
– 191 peripheral interrupt request sources, plus 165
reserved positions
– Low latency—three clocks from receipt of interrupt
request from peripheral to interrupt request to processor
• Frequency Modulating Phase-locked loop (FMPLL)
• Calibration bus interface (EBI) (available only in the
calibration package)
• System integration unit (SIU) centralizes control of pads,
GPIO pins and external interrupts.
• Error correction status module (ECSM) provides
configurable error-correcting codes (ECC) reporting
• Up to 1.5 MB on-chip flash memory
• Up to 94 KB on-chip static RAM
• Boot assist module (BAM) enables and manages the
transition of MCU from reset to user code execution from
internal flash memory, external memory on the calibration
bus or download and execution of code via FlexCAN or
eSCI.
• Periodic interrupt timer (PIT)
176 LQFP
24 mm x 24 mm
•
•
•
•
•
•
•
•
•
•
– 32-bit wide down counter with automatic reload
– 4 channels clocked by system clock
– 1 channel clocked by crystal clock
System timer module (STM)
– 32-bit up counter with 8-bit prescaler
– Clocked from system clock
– 4 channel timer compare hardware
Software watchdog timer (SWT) 32-bit timer
Enhanced modular I/O system (eMIOS)
– 16 standard timer channels (up to 14 channels connected
to pins in LQFP144)
– 24-bit timer resolution
Second-generation enhanced time processor unit (eTPU2)
– High level assembler/compiler
– Enhancements to make ‘C’ compiler more efficient
– New ‘engine relative’ addressing mode
Enhanced queued A/D converter (eQADC)
– 2 independent on-chip RSD Cyclic ADCs
– Up to 34 input channels available to the two on-chip
ADCs
– 4 pairs of differential analog input channels
2 deserial serial peripheral interface modules (DSPI)
– SPI provides full duplex communication ports with
interrupt and DMA request support
– Deserial serial interface (DSI) achieves pin reduction by
hardware serialization and deserialization of eTPU,
eMIOS channels and GPIO
2 enhanced serial communication interface (eSCI) modules
2 FlexCAN modules
Nexus port controller (NPC) per IEEE-ISTO 5001-2003
standard
IEEE 1149.1 JTAG controller (JTAGC)
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008, 2009. All rights reserved.
Preliminary—Subject to Change Without Notice
Table of Contents
1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 MPC5634M features . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 MPC5634M feature details . . . . . . . . . . . . . . . . . . . . . .11
1.3.1 e200z335 core . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.3.2 Crossbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.3.3 eDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.3.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . .13
1.3.5 FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.3.6 Calibration EBI. . . . . . . . . . . . . . . . . . . . . . . . . .15
1.3.7 SIU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.3.8 ECSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.3.9 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.3.10 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.3.11 BAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.3.12 eMIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.3.13 eTPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.3.14 eQADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.3.15 DSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.3.16 eSCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.3.17 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.3.18 System timers . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.3.19 Software Watchdog Timer (SWT) . . . . . . . . . . .25
1.3.20 Nexus Port Controller . . . . . . . . . . . . . . . . . . . .25
1.3.21 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.4 MPC5634M series architecture. . . . . . . . . . . . . . . . . . .28
1.4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.4.2 Block summary . . . . . . . . . . . . . . . . . . . . . . . . .29
Pinout and signal description . . . . . . . . . . . . . . . . . . . . . . . . .29
2.1 144 LQFP pinout (all 144-pin devices) . . . . . . . . . . . . .30
2.2 176 LQFP pinout (MPC5634M) . . . . . . . . . . . . . . . . . .31
2.3 176 LQFP pinout (MPC5633M) . . . . . . . . . . . . . . . . . .32
2.4 MAPBGA208 ballmap (MPC5634M). . . . . . . . . . . . . . .33
2.5 MAPBGA208 ballmap (MPC5633M only) . . . . . . . . . . .34
2.6 Signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.7 Signal Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Parameter classification. . . . . . . . . . . . . . . . . . . . . . . . 57
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60
3.3.1 General notes for specifications at maximum
junction temperature. . . . . . . . . . . . . . . . . . . . . 61
3.4 EMI (Electromagnetic Interference) characteristics . . . 64
3.5 Electromagnetic static discharge (ESD) characteristics64
3.6 Power Management Control (PMC) and Power On Reset
(POR) electrical specifications. . . . . . . . . . . . . . . . . . . 65
3.6.1 Regulator example . . . . . . . . . . . . . . . . . . . . . . 69
3.6.2 Recommended power transistors. . . . . . . . . . . 69
3.7 Power up/down sequencing. . . . . . . . . . . . . . . . . . . . . 70
3.8 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . 70
3.9 I/O Pad current specifications . . . . . . . . . . . . . . . . . . . 77
3.9.1 I/O pad VRC33 current specifications . . . . . . . 78
3.9.2 LVDS pad specifications. . . . . . . . . . . . . . . . . . 80
3.10 Oscillator and PLLMRFM electrical characteristics . . . 81
3.11 Temperature sensor electrical characteristics . . . . . . . 83
3.12 eQADC electrical characteristics . . . . . . . . . . . . . . . . . 83
3.13 Platform flash controller electrical characteristics . . . . 84
3.14 Flash memory electrical characteristics . . . . . . . . . . . 85
3.15 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.15.1 Pad AC specifications. . . . . . . . . . . . . . . . . . . . 86
3.16 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.16.1 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 90
3.16.2 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.16.3 Calibration bus interface timing . . . . . . . . . . . . 96
3.16.4 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.16.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.16.6 eQADC SSI timing . . . . . . . . . . . . . . . . . . . . . 105
Mechanical outline drawings . . . . . . . . . . . . . . . . . . . . . . . . 105
4.1 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.2 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.3 208 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.1
3.2
3.3
2
4
5
6
3
MPC5634M Microcontroller Data Sheet, Rev. 4
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
1
Overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5634M series of
microcontroller units (MCUs). For functional characteristics, refer to the MPC5634M
Microcontroller Reference Manual.
The MPC5634M series microcontrollers are system-on-chip devices that are built on Power Architecture
TM
technology and:
•
•
•
•
Are 100% user-mode compatible with the Power Architecture instruction set
Contain enhancements that improve the architecture’s fit in embedded applications
Include additional instruction support for digital signal processing (DSP)
Integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter,
Controller Area Network, and an enhanced modular input-output system
1.1
Device comparison
Table 1. MPC5634M family device summary
Feature
Flash memory size (KB)
Total RAM size (KB)
Standby RAM size (KB)
Processor core
Core frequency (MHz)
Calibration bus width
1
DMA (direct memory access) channels
eMIOS (enhanced modular input-output system)
channels
eQADC (enhanced queued analog-to-digital
converter) channels (on-chip)
eSCI (serial communication interface)
DSPI (deserial serial peripheral interface)
Microsecond Bus compatible interface
eTPU (enhanced time processor unit)
Channels
Code memory (KB)
Parameter RAM (KB)
FlexCAN (controller area network)
3
FMPLL (frequency-modulated phase-locked loop)
INTC (interrupt controller) channels
JTAG controller
NDI (Nexus development interface) level
Non-maskable interrupt and critical interrupt
MPC5634M
1536
94
32
32-bit e200z335
with SPE support
60/80
16 bits
32
16
Up to 34
2
2
2
2
Yes
32
14
3
2
Yes
364
4
Yes
Class 2+
Yes
MPC5633M
1024
64
24
32-bit e200z335
with SPE support
40/60/80
16 bits
32
16
Up to 34
2
2
2
2
Yes
32
14
3
2
Yes
364
4
Yes
Class 2+
Yes
MPC5632M
768
48
24
32-bit e200z335
with SPE support
40/60
—
32
8
Up to 32
2
2
2
2
Yes
32
14
3
2
Yes
364
4
Yes
Class 2+
Yes
MPC5634M Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
Overview
Table 1. MPC5634M family device summary (continued)
Feature
PIT (peripheral interrupt timers)
Task monitor timer
Temperature sensor
Windowing software watchdog
Packages
MPC5634M
5
4 channels
Yes
Yes
144 LQFP
176 LQFP
208 MAPBGA
MPC5633M
5
4 channels
Yes
Yes
144 LQFP
176 LQFP
208 MAPBGA
MPC5632M
5
4 channels
Yes
Yes
144 LQFP
1
2
Calibration package only
The 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32.
3
One FlexCAN module has 64 message buffers; the other has 32 message buffers.
4
165 interrupt channels are reserved for compatibility with future devices. This device has 191 peripheral interrupt
sources plus 8 software interrupts available to the user.
1.2
•
MPC5634M features
Operating Parameters
— Fully static operation, 0 MHz – 80 MHz (plus 2% frequency modulation - 82 MHz)
— -40 °C to 150 °C junction temperature operating range
— Low power design
– Less than 400 mW power dissipation (nominal)
– Designed for dynamic power management of core and peripherals
– Software controlled clock gating of peripherals
– Low power stop mode, with all clocks stopped
— Fabricated in 90 nm process
— 1.2 V internal logic
— Single power supply with 5.0 V
−10%/+5%
(4.5 V to 5.25 V) with internal regulator to provide 3.3 V and 1.2 V
for the core
— Input and output pins with 5.0 V
−10% / +5%
(4.5 V to 5.25 V) range
– 35%/65% V
DDE
CMOS switch levels (with hysteresis)
– Selectable hysteresis
– Selectable slew rate control
— Nexus pins powered by 3.3 V supply
— Designed with EMI reduction techniques
– Phase-locked loop
– Frequency modulation of system clock frequency
– On-chip bypass capacitance
– Selectable slew rate and drive strength
High performance e200z335 core processor
— 32-bit
Power Architecture Book E
programmer’s model
— Variable Length Encoding Enhancements
– Allows Power Architecture instruction set to be optionally encoded in a mixed 16 and 32-bit instructions
– Results in smaller code size
— Single issue, 32-bit
Power Architecture Book E
compliant CPU
MPC5634M Microcontroller Data Sheet, Rev. 4
•
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
•
•
— In-order execution and retirement
— Precise exception handling
— Branch processing unit
– Dedicated branch address calculation adder
– Branch acceleration using Branch Lookahead Instruction Buffer
— Load/store unit
– One-cycle load latency
– Fully pipelined
– Big and Little Endian support
– Misaligned access support
– Zero load-to-use pipeline bubbles
— Thirty-two 64-bit general purpose registers (GPRs)
— Memory management unit (MMU) with 8-entry fully-associative translation look-aside buffer (TLB)
— Separate instruction bus and load/store bus
— Vectored interrupt support
— Interrupt latency < 120 ns @ 80 MHz (measured from interrupt request to execution of first instruction of interrupt
exception handler)
— Non-maskable interrupt (NMI) input for handling external events that must produce an immediate response, e.g.,
power down detection. On this device, the NMI input is connected to the Critical Interrupt Input. (May not be
recoverable)
— Critical Interrupt input. For external interrupt sources that are higher priority than provided by the Interrupt
Controller. (Always recoverable)
— New ‘Wait for Interrupt’ instruction, to be used with new low power modes
— Reservation instructions for implementing read-modify-write accesses
— Signal processing extension (SPE) APU
– Operating on all 32 GPRs that are all extended to 64 bits wide
– Provides a full compliment of vector and scalar integer and floating point arithmetic operations (including
integer vector MAC and MUL operations) (SIMD)
– Provides rich array of extended 64-bit loads and stores to/from extended GPRs
– Fully code compatible with e200z6 core
— Floating point
– IEEE 754 compatible with software wrapper
– Scalar single precision in hardware, double precision with software library
– Conversion instructions between single precision floating point and fixed point
– Fully code compatible with e200z6 core
— Long cycle time instructions, except for guarded loads, do not increase interrupt latency
— Extensive system development support through Nexus debug port
Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)
— Three master ports, four slave ports
– Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA
– Slave: Flash; SRAM; Peripheral Bridge; calibration EBI
— 32-bit internal address bus, 64-bit internal data bus
Enhanced direct memory access (eDMA) controller
— 32 channels support independent 8-bit, 16-bit, or 32-bit single value or block transfers
— Supports variable sized queues and circular queues
— Source and destination address registers are independently configured to post-increment or remain constant
MPC5634M Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
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