8:1, DIFFERENTIAL-TO-3.3V or 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
ICS853058
Features
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High speed 8:1 differential muliplexer
One differential 3.3V or 2.5V LVPECL output
Eight selectable differential PCLKx/nPCLKx input pairs
Differential PCLKx/nPCLKx pairs can accept the following
interface levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: 2.8GHz
Translates any single ended input signal to LVPECL levels with
resistor bias on nPCLKx input
RMS phase jitter @ 155.52MHz: 0.212ps (typical)
Part-to-part skew: 325ps (maximum)
Propagation delay: 450ps (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.465V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.465V to -2.375V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
General Description
he ICS853058 is an 8:1 Differential-to-3.3V or 2.5V
LVPECL / ECL Clock Multiplexer which can operate
HiPerClockS™
up to 2.8GHz and is a member of the HiPerClockS™
family of High Performance Clock Solutions from
IDT. The ICS853058 has 8 differential selectable
clock inputs. The PCLK, nPCLK input pairs can accept LVPECL,
LVDS, CML or SSTL levels. The fully differential architecture and
low propagation delay make it ideal for use in clock distribution
circuits. The select pins have internal pulldown resistors. The
SEL2 pin is the most significant bit and the binary number applied
to the select pins will select the same numbered data input (i.e.,
000 selects PCLK0, nPCLK0).
ICS
Block Diagram
PCLK0
Pulldown
nPCLK0
Pullup/Pulldown
PCLK1
Pulldown
nPCLK1
Pullup/Pulldown
PCLK2
Pulldown
Pullup/Pulldown
000
Pin Assignment
PCLK0
nPCLK0
PCLK1
nPCLK1
V
CC
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PCLK7
nPCLK7
PCLK6
nPCLK6
V
CC
Q
nQ
V
EE
PCLK5
nPCLK5
PCLK4
nPCLK4
001
Q
nQ
010
nPCLK2
PCLK3
Pulldown
nPCLK3
Pullup/Pulldown
PCLK0
Pulldown
nPCLK0
Pullup/Pulldown
PCLK1
Pulldown
nPCLK1
Pullup/Pulldown
PCLK2
Pulldown
nPCLK2
Pullup/Pulldown
PCLK3
Pulldown
nPCLK3
Pullup/Pulldown
011
100
ICS853S057I
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
101
110
111
Pulldown
Pulldown
SEL1 SEL1 SEL0
IDT™ / ICS™
3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
Pulldown
1
ICS853058AG REV. A MAY 12, 2008
ICS853058
8:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5, 20
6, 7, 8
9
10
11
12
13
14
15
16
17
18, 19
21
22
23
24
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
V
CC
SEL0, SEL1, SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
nPCLK4
PCLK4
nPCLK5
PCLK5
V
EE
nQ, Q
nPCLK6
PCLK6
nPCLK7
PCLK7
Input
Input
Input
Input
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power
Output
Input
Input
Input
Input
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Type
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Positive supply pins.
Clock select input pins. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLDOWN
R
VCC/2
Parameter
Pulldown Resistor
Pullup/Pulldown Resistor
Test Conditions
Minimum
Typical
75
50
Maximum
Units
k
Ω
k
Ω
IDT™ / ICS™
3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
2
ICS853058AG REV. A MAY 12, 2008
ICS853058
8:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
Function Tables
Table 3. Control Input Function Table
Inputs
SEL2
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Q
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
Outputs
nQ
nPCLK0
nPCLK1
nPCLK2
nPCLK3
nPCLK4
nPCLK5
nPCLK6
nPCLK7
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuos Current
Surge Current
Operating Temperature Range, T
A
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
5.5V (LVPECL mode, V
EE
= 0V)
-5.5V (ECL mode, V
CC
= 0V)
-0.5V to V
CC
+ 0.5V
0.5V to V
EE
– 0.5V
50mA
100mA
-40°C to +85°C
70°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 2.375V to 3.465V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.465
47
Units
V
mA
IDT™ / ICS™
3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
3
ICS853058AG REV. A MAY 12, 2008
ICS853058
8:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 2.375V to 3.465V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SEL[0:2]
SEL[0:2]
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
Table 4C. LVPECL DC Characteristics,
V
CC
= 2.375V to 3.465V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Parameter
Input High
Current
Input Low
Current
PCLK[0:7],
nPCLK[0:7]
PCLK[0:7]
nPCLK[0:7]
Test Conditions
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
-150
0.15
1.2
V
CC
– 1.125
V
CC
– 1.895
0.6
1.5
V
CC
V
CC
– 0.935
V
CC
– 1.670
1.0
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
V
V
Peak-to-Peak Input Voltage
Common Mode Range;
NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Peak-to-Peak
Output Voltage Swing
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: V
IL
should not be less than -0.3V.
NOTE 3: Outputs terminated with 50
Ω
to V
CC
– 2V
Table 4D. ECL DC Characteristics,
V
CC
= 0V, V
EE
= -3.465V to -2.375V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
PP
V
CMR
I
IH
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
Input High Voltage Common Mode
Range; NOTE 2, 3
Input
High Current
Input
Low Current
PCLK[0:7],
nPCLK[0:7]
PCLK[0:7]
nPCLK[0:7]
NOTE 1: Outputs terminated with 50
Ω
to V
CC
– 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: V
IL
should not be less than -0.3V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
Test Conditions
Minimum
-1.225
-1.895
0.15
V
EE
+ 1.2
Typical
Maximum
-0.935
-1.67
1.5
0
150
-10
-150
Units
V
V
V
V
µA
µA
µA
I
IL
IDT™ / ICS™
3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
4
ICS853058AG REV. A MAY 12, 2008
ICS853058
8:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
AC Electrical Characteristics
Table 5. AC Characteristics,
V
CC
= 0V, V
EE
= -3.465V to -2.375V or V
CC
= 2.375 to 3.465V, T
A
= -40°C to 85°C
Symbol
f
MAX
tjit
t
PD
tsk(pp)
tsk(i)
t
R
/ t
F
MUX
ISOLATION
Parameter
Output Frequency
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter section
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Input Skew
Output Rise/Fall Time
MUX Isolation
20% to 80%
155.52MHz,
Input Peak-to-Peak = 800mV
75
-55
155.52MHz,
12kHz – 20MHz
125
0.212
450
325
75
220
Test Conditions
Minimum
Typical
Maximum
2.8
Units
GHz
ps
ps
ps
ps
ps
dB
All parameters measured up to 1.3GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
IDT™ / ICS™
3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
5
ICS853058AG REV. A MAY 12, 2008
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