EEWORLDEEWORLDEEWORLD

Part Number

Search

8S89874BKILFT

Description
VFQFPN-16, Reel
Categorylogic    logic   
File Size647KB,21 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric Compare View All

8S89874BKILFT Online Shopping

Suppliers Part Number Price MOQ In stock  
8S89874BKILFT - - View Buy Now

8S89874BKILFT Overview

VFQFPN-16, Reel

8S89874BKILFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeVFQFPN
package instructionVFQFN-16
Contacts16
Manufacturer packaging codeNLG16P2
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionVFQFN- N 3 X 3 X 1.0 MM - NO LEAD
series8S
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeS-XQCC-N16
JESD-609 codee3
length3 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level3
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times2
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC16,.12SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3 V
Prop。Delay @ Nom-Sup0.84 ns
propagation delay (tpd)0.84 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.015 ns
Maximum seat height1 mm
Maximum supply voltage (Vsup)3.63 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width3 mm
minfmax2000 MHz
Base Number Matches1
1:2 Differential-to-LVPECL
Buffer/Divider
Data Sheet
8S89874
General Description
The 8S89874 is a high speed 1:2 Differential-to- LVPECL Buffer/
Divider. The 8S89874 has a selectable ÷1, ÷2, ÷4, ÷8, ÷16 output
divider, which allows the device to be used as either a 1:2 fanout
buffer or frequency divider. The clock input has internal termination
resistors, allowing it to interface with several differential signal types
while minimizing the number of required external components. The
device is packaged in a small, 3mm x 3mm VFQFN package, making
it ideal for use on space-constrained boards.
Features
Two LVPECL/ECL output pairs
Frequency divide select options: ÷1 (pass through), ÷2, ÷4, ÷8,
÷16
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
Output frequency: 2GHz (maximum)
Output skew: 15ps (maximum)
Part-to-part skew: 250ps (maximum)
Additive phase jitter, RMS: 0.20ps (typical)
LVPECL supply voltage range: 2.375V to 3.63V
ECL supply voltage range: -3.63V to -2.375V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
S2
Pullup
Pin Assignment
V
CC
14
nRESET
Pullup
Enable
FF
Enable
MUX
Q0
0
nQ0
Q0
nQ0
Q1
Q1
nQ1
1
2
3
4
16
15
V
EE
13
12
11
S0
S1
IN
V
T
V
REF_AC
nIN
8S89874
1
IN
50Ω
8XXXXXX
5
6
7
8
10
9
V
T
nIN
50Ω
S0
Pullup
S1
Pullup
V
REF_AC
Decoder
16-pin, 3mm x 3mm VFQFN Package
©2016 Integrated Device Technology, Inc
1
Revision B February 9, 2016
nRESET
V
CC
S2
nc
00
01
10
11
÷2
÷4
÷8
÷16
nQ1

8S89874BKILFT Related Products

8S89874BKILFT 8S89874BKILF 8S89874BKILF/W
Description VFQFPN-16, Reel VFQFPN-16, Tube VFQFPN-16, Reel
Brand Name Integrated Device Technology Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free Lead free
Is it Rohs certified? conform to conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code VFQFPN VFQFPN VFQFPN
package instruction VFQFN-16 VFQFN-16 HVQCCN,
Contacts 16 16 16
Manufacturer packaging code NLG16P2 NLG16P2 NLG16P2
Reach Compliance Code compliant compliant compliant
ECCN code EAR99 EAR99 EAR99
Samacsys Description VFQFN- N 3 X 3 X 1.0 MM - NO LEAD VFQFN- N 3 X 3 X 1.0 MM - NO LEAD VFQFN- N 3 X 3 X 1.0 MM - NO LEAD
series 8S 8S 8S8987
Input adjustment DIFFERENTIAL MUX DIFFERENTIAL MUX DIFFERENTIAL MUX
JESD-30 code S-XQCC-N16 S-XQCC-N16 S-XQCC-N16
JESD-609 code e3 e3 e3
length 3 mm 3 mm 3 mm
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Humidity sensitivity level 3 3 3
Number of functions 1 1 1
Number of terminals 16 16 16
Actual output times 2 2 4
Maximum operating temperature 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Package body material UNSPECIFIED UNSPECIFIED UNSPECIFIED
encapsulated code HVQCCN HVQCCN HVQCCN
Package shape SQUARE SQUARE SQUARE
Package form CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260 260
propagation delay (tpd) 0.84 ns 0.84 ns 0.84 ns
Same Edge Skew-Max(tskwd) 0.015 ns 0.015 ns 0.015 ns
Maximum seat height 1 mm 1 mm 1 mm
Maximum supply voltage (Vsup) 3.63 V 3.63 V 3.63 V
Minimum supply voltage (Vsup) 2.375 V 2.375 V 2.375 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V
surface mount YES YES YES
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn)
Terminal form NO LEAD NO LEAD NO LEAD
Terminal pitch 0.5 mm 0.5 mm 0.5 mm
Terminal location QUAD QUAD QUAD
Maximum time at peak reflow temperature 30 30 NOT SPECIFIED
width 3 mm 3 mm 3 mm
minfmax 2000 MHz 2000 MHz 2000 MHz
Encapsulate equivalent code LCC16,.12SQ,20 LCC16,.12SQ,20 -
power supply 2.5/3.3 V 2.5/3.3 V -
Prop。Delay @ Nom-Sup 0.84 ns 0.84 ns -
Certification status Not Qualified Not Qualified -
Basic steps for inverter debugging
1. No-load power-on test of the inverter 11 Ground the ground terminal of the inverter. 21 Connect the power input terminal of the inverter to the power supply through the leakage protection switch. 3...
comeon365 Industrial Control Electronics
MSP430 MCU controls IO port operation - LED flashes.doc
MSP430 entry-level routine!...
wpdy Microcontroller MCU
Image Acquisition and Recognition System Based on TMS320VC5509A
Image Acquisition and Recognition System Based on TMS320VC5509A...
shaomingyi DSP and ARM Processors
[Rawpixel RVB2601 development board trial experience] 4. General hardware timer test
4. General Hardware Timer TestWhen using an operating system, if some tasks are performed in a software dead-wait manner, the system efficiency will inevitably be affected. Therefore, some slow period...
gs001588 XuanTie RISC-V Activity Zone
ADC, after 32 conversions, the digital tube stops displaying. What's the problem?
[i=s]This post was last edited by dontium on 2015-1-23 12:51[/i]/******************************************* ADC conversion channel port is P1.1. When the analog value of this program is greater than ...
flyingheartt Analogue and Mixed Signal
Ask a question about Verilog
I am a FPGA newbie, and now I have a Verilog question I would like to ask For example, there is an input data input [16:0] REG For ease of use, I now want to disassemble REG, such as a = REG[16:8]; b ...
littleshrimp FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1083  125  1148  1581  184  22  3  24  32  4 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号