Differential-to-0.7V HCSL Differential
PCI EXPRESS™ Jitter Attenuator
General Description
The ICS871002I-02 is a high performance Jitter
Attenuator designed for use in PCI Express™systems.
HiPerClockS™
In some PCI Express systems, such as those found in
desktop PCs, the PCI Express clocks are generated
from a low bandwidth, high phase noise PLL frequency
synthesizer. In these systems, a jitter attenuator may be required to
attenuate high frequency random and deterministic jitter components
from the PLL synthesizer and from the system board. The
ICS871002I-02 has two PLL bandwidth modes: 350kHz and
2200kHz. The 350kHz mode provides the maximum jitter
attenuation, but it also results in higher PLL tracking time. In this
mode, the spread spectrum modulation may also be attenuated. The
2200kHz bandwidth provides the best tracking skew and will pass
most spread profiles, but the jitter attenuation will not be as good as
the lower bandwidth modes. The ICS871002I-02 can be set for
different modes using the F_SELx pins as shown in Table 3C.
ICS871002I-02
DATA SHEET
Features
•
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Two 0.7V HCSL differential output pairs
One differential clock input
CLK, nCLK can accept the following differential input levels:
LVPECL, LVDS, HSTL, HCSL, SSTL
Input frequency range: 98MHz to 128MHz
Output frequency range: 98MHz to 640MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 45ps (maximum)
Two bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
The ICS871002I-02 uses IDT 3
rd
Generation FemtoClock
TM
PLL
technology to achieve the lowest possible phase noise. The
device is packaged in a small 20 Lead TSSOP package, making it
ideal for use in space constrained applications such as PCI Express
add-in cards.
PLL Bandwidth (typical) Table
BW_SEL
0 = PLL Bandwidth: ~350kHz (default)
1 = PLL Bandwidth: ~2200kHz
Block Diagram
IREF
OE
Pullup
F_SEL[1:0]
Pullup:Pulldown
2
Pin Assignment
nQ0
IREF
FB_OUT
nFB_OUT
MR
BW_SEL
F_SEL1
V
DDA
F_SEL0
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
V
DD
Q1
nQ1
nFB_IN
FB_IN
GND
nCLK
CLK
OE
BW_SEL
Pulldown
0 = 350kHz
1 = 2200kHz
CLK
Pulldown
nCLK
Pullup
Phase
Detector
VCO
490 - 640 MHz
Output Divider
00 ÷5
01 ÷4
10 ÷2 (default)
11 ÷1
Q0
nQ0
Q1
nQ1
FB_IN
Pulldown
nFB_IN
Pullup
ICS871002I-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
÷5 (fixed)
FB_OUT
nFB_OU
MR
Pulldown
ICS871002AGI-02 REVISION A APRIL 14, 2010
1
©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Table 1. Pin Descriptions
Number
1, 20
2
3,
4
Name
nQ0, nQ0
IREF
FB_OUT,
nFB_OUT
Output
Input
Output
Type
Description
Differential output pair. HCSL interface levels.
A fixed precision resistor (475
Ω
) from this pin to ground provides a reference
current used for differential current-mode Qx/nQx clock outputs.
Differential feedback output pair. HCSL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs (Qx, FB_OUT) to go low and the inverted outputs (nQx,
nFB_OUT) to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
PLL Bandwidth select input. 0 = 350kHz, 1 = 2200kHz. See Table 3B.
Frequency select pins. See Table 3C. LVCMOS/LVTTL interface levels
Analog supply pin.
Core supply pins.
Pullup
Pulldown
Pullup
Pulldown
Pullup
Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are
in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A.
Non-inverting differential clock input.
Inverting differential clock input.
Power supply ground.
Non-inverting differential feedback clock input.
Inverting differential feedback clock input.
Differential output pair. HCSL interface levels.
5
MR
Input
Pulldown
6
7,
9
8
10, 19
11
12
13
14
15
16
17, 18
BW_SEL
F_SEL1,
F_SEL0
V
DDA
V
DD
OE
CLK
nCLK
GND
FB_IN
nFB_IN
nQ1, Q1
Input
Input
Power
Power
Input
Input
Input
Power
Input
Input
Output
Pulldown
Pullup
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS871002AGI-02 REVISION A APRIL 14, 2010
2
©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Function Tables
Table 3A. Output Enable Function Table
Input
OE
0
1 (default)
Q[1:0], nQ[1:0]
High-Impedance
Enabled
Outputs
FB_OUT, nFB_OUT
Enabled
Enabled
Table 3B. PLL Bandwidth Control Table
Input
BW_SEL
0
1
PLL Bandwidth
350kHz (default)
2200kHz
Table 3C. F_SELx Function Table
Input Frequency
(MHz)
100
100
100
100
Inputs
F_SEL1
0
0
1
1
F_SEL0
0
1
0
1
Divider
÷5
÷4
÷2
÷1
Output Frequency
(MHz)
100
125
250 (default)
500
ICS871002AGI-02 REVISION A APRIL 14, 2010
3
©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
86.7°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.97
V
DD
– 0.12
Typical
3.3
3.3
Maximum
3.63
V
DD
75
12
Units
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
OE, F_SEL1
Input High Current
BW_SEL,
F_SEL0, MR
OE, F_SEL1
I
IL
Input Low Current
BW_SEL,
F_SEL0, MR
V
DD
= V
IN
= 3.63V
V
DD
= V
IN
= 3.63V
V
DD
= 3.63V, V
IN
= 0V
V
DD
= 3.63V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
Table 4C. Differential DC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
CLK, FB_IN
Input High Current
nCLK, nFB_IN
CLK, FB_IN
I
IL
V
PP
V
CMR
Input Low Current
nCLK, nFB_IN
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
ICS871002AGI-02 REVISION A APRIL 14, 2010
4
©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Table 5. 0.7V HCSL Differential AC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
f
MAX
tjit(cc)
V
MAX
V
MIN
V
RB
V
CROSS
∆V
CROSS
t
R
/ t
F
odc
Parameter
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
Absolute Max. Output Voltage;
NOTE 2, 3
Absolute Min. Output Voltage;
NOTE 2, 4
Ringback Voltage; NOTE 5, 6
Absolute Crossing Voltage;
NOTE 2, 7, 8
Total Variation of V
CROSS
over
all edges; NOTE 2, 7, 9
Output Rise/Fall Time
Output Duty Cycle; NOTE 10
measured between -150mV to +150mV
0.6
48
-300
-100
200
100
550
140
4.75
52
PLL Mode
Test Conditions
Minimum
98
Typical
Maximum
640
45
1150
Units
MHz
ps
mV
mV
mV
mV
mV
V/ns
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at f
≤
250MHz unless noted otherwise.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Measurement taken from single ended waveform.
NOTE 3: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 4: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 5: Measurement taken from differential waveform.
NOTE 6:T
STABLE
is the time the differential clock must maintain a minimum ± 150mV differential voltage after rising/falling edges before it is
allowed to drop back into the V
RB
±100mV differential range.
NOTE 7: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.
NOTE 8: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
NOTE 9: Defined as the total variation of all crossing voltages of rising Q and falling nQ, This is the maximum allowed variance in Vcross for
any particular system.
NOTE 10: Input duty cycle must be 50%.
ICS871002AGI-02 REVISION A APRIL 14, 2010
5
©2010 Integrated Device Technology, Inc.
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