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854S204BGILFT

Description
TSSOP-16, Reel
Categorylogic    logic   
File Size2MB,24 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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854S204BGILFT Overview

TSSOP-16, Reel

854S204BGILFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP16,.25
Contacts16
Manufacturer packaging codePGG16
Reach Compliance Codecompliant
ECCN codeEAR99
series854
Input adjustmentDIFFERENTIAL
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length5 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level1
Number of functions2
Number of inverted outputs
Number of terminals16
Actual output times2
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3 V
Prop。Delay @ Nom-Sup0.5 ns
propagation delay (tpd)0.5 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.015 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
Base Number Matches1
Low Skew, Dual, Programmable 1-to-2
Differential-to-LVDS, LVPECL Fanout Buffer
ICS854S204I
DATA SHEET
General Description
The ICS854S204I is a low skew, high performance dual,
programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer.
The PCLKx, nPCLKx pairs can accept most standard differential
input levels. With the selection of SEL_OUT signal, outputs can be
selected be to either LVDS or LVPECL levels. The ICS854S204I is
characterized to operate from either a 2.5V or a 3.3V power supply.
Guaranteed output and bank skew characteristics make the
ICS854S204I ideal for those clock distribution applications
demanding well defined performance and repeatability.
Features
Two programmable differential LVDS or LVPECL output banks
Two differential clock input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, SSTL, CML
Maximum output frequency: 3GHz
Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx inputs
Output skew: 15ps (maximum)
Bank skew: 15ps (maximum)
Propagation delay: 500ps (maximum)
Additive phase jitter, RMS: 0.15ps (typical)
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Power Supply Configuration Table
3.3V Operation
V
DD
= 3.3V
V
TAP
= nc
2.5V Operation
V
DD
= 2.5V
V
TAP
= 2.5V
SEL_OUT Function Table
SEL_OUT
0
1
Output Level
LVDS
LVPECL
Block Diagram
V
TAP
SEL_OUT
Pulldown
CLKA
Pulldown
nCLKA
Pullup
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
Pin Assignment
PCLKA
nPCLKA
QA0
nQA0
QA1
nQA1
V
TAP
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
nPCLKB
PCLKB
QB0
nQB0
QB1
nQB1
V
DD
SEL_OUT
CLKB
Pulldown
nCLKB
Pullup
ICS854S204I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS854S204BGI REVISION B NOVEMBER 18, 2011
1
©2011 Integrated Device Technology, Inc.
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