Integrated
Circuit
Systems, Inc.
ICS8634-01
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
F
EATURES
•
Five differential 3.3V LVPECL outputs
•
Selectable differential clock inputs
•
CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
Output frequency range: 31.25MHz to 700MHz
•
Input frequency range: 31.25MHz to 700MHz
•
VCO range: 250MHz to 700MHz
•
External feedback for “zero delay” clock regeneration
•
Cycle-to-cycle jitter: 25ps (maximum)
•
Output skew: 25ps (maximum)
•
PLL reference zero delay: 50ps ± 100ps
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Lead-Free package available
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS8634-01 is a high performance 1-to-5 Dif-
ferential-to-3.3V LVPECL Zero Delay Buffer and a
HiPerClockS™
member of the HiPerClockS™ family of High Per-
formance Clock Solutions from ICS. The ICS8634-
01 has two selectable clock inputs. The CLKx,
nCLKx pair can accept most standard differential input levels.
Utilizing one of the outputs as feedback to the PLL, output fre-
quencies up to 700MHz can be regenerated with zero delay with
respect to the input. Dual reference clock inputs support redun-
dant clock or multiple reference applications.
IC
S
B
LOCK
D
IAGRAM
Q0
nQ0
PLL_SEL
÷4, ÷8
0
1
1
Q3
nQ3
Q1
nQ1
0
Q2
nQ2
P
IN
A
SSIGNMENT
PLL_SEL
V
CCO
V
CCA
nQ4
V
CC
V
EE
V
EE
Q4
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
32 31 30 29 28 27 26 25
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
CC
nFB_IN
FB_IN
V
EE
V
EE
nQ0
Q0
V
CCO
24
23
22
V
CCO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
CCO
PLL
Q4
nQ4
ICS8634-01
21
20
19
18
17
SEL0
SEL1
MR
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32-Lead VFQFN
5mm x 5mm x 0.95 package body
K Package
Top View
8634BY
-01
www.icst.com/products/hiperclocks.html
1
REV. D APRIL 12, 2007
Integrated
Circuit
Systems, Inc.
ICS8634-01
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
Type
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
Name
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
Input
Input
Input
Input
Input
Input
Input
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Pullup
Inver ting differential clock input.
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Clock select input. When LOW, selects CLK0, nCLK0.
Pulldown
When HIGH, selects CLK1, nCLK1. LVCMOS / LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inver ted outputs nQx to go
Pulldown
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Core supply pins.
Pullup
Feedback input to phase detector for regenerating clocks with "zero delay".
Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
Negative supply pins.
Differential output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels..
Differential output pair. LVPECL interface levels.
Analog supply pin.
Selects between the PLL and the reference clock as the input to the dividers.
When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS /
LVTTL interface levels.
8
9, 32
10
11
12, 13
28, 29
14, 15
16. 17,
24, 25
18, 19
20, 21
22, 23
26, 27
30
31
MR
V
CC
nFB_IN
FB_IN
V
EE
nQ0, Q0
V
CCO
nQ1, Q1
nQ2, Q2
nQ3, Q3
nQ4, Q4
V
CCA
PLL_SEL
Input
Power
Input
Input
Power
Output
Power
Output
Output
Output
Output
Power
Input
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
SEL1 SEL0
0
0
1
0
1
0
Reference Frequency Range (MHz)*
250 - 700
125 - 350
62.5 - 175
Outputs
PLL_SEL = 1
PLL Enable Mode
Q0:Q4, nQ0:nQ4
÷1
÷1
÷1
÷1
T
ABLE
3B. PLL B
YPASS
F
UNCTION
T
ABLE
Inputs
SEL1 SEL0
0
0
1
1
0
1
0
1
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q0:Q4, nQ0:nQ4
÷4
÷4
÷4
÷8
1
1
31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is
250MHz to 700MHz.
8634BY
-01
www.icst.com/products/hiperclocks.html
2
REV. D APRIL 12, 2007
Integrated
Circuit
Systems, Inc.
ICS8634-01
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
34.8°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
32 Lead LQFP
32 Lead VFQFN
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
150
15
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input High Current
SEL0, SEL1,
CLK_SEL, MR
PLL_SEL
I
IL
Input Low Current
SEL0, SEL1,
CLK_SEL, MR
PLL_SEL
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
15 0
5
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
0.15
1.3
Minimum Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
V
CMR
Common Mode Input Voltage; NOTE 1, 2
V
EE
+ 0.5
V
CC
- 0.85
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
8634BY
-01
www.icst.com/products/hiperclocks.html
3
REV. D APRIL 12, 2007
Integrated
Circuit
Systems, Inc.
ICS8634-01
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0. 6
Typical
Maximum
V
CCO
- 0.7
V
CCO
- 1.7
1.0
Units
V
V
V
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
IN
Parameter
Input Frequency
CLK0, nCLK0,
CLK1, nCLK1
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
31.25
Typical
Maximum
700
700
Units
MHz
MHz
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
t
(Ø)
t
sk(o)
t
jit(cc)
t
jit(
θ)
t
L
t
R
/ t
F
Parameter
Output Frequency
Propagation Delay; NOTE 1
PLL Reference Zero Delay;
NOTE 2, 4
Output Skew; NOTE 3, 4
Cycle-to-Cycle Jitter; NOTE 4, 6
Phase Jitter; NOTE 4, 5, 6
PLL Lock Time
Output Rise/Fall Time
20% to 80% @ 50MHz
300
PLL_SEL = 0V,
f
≤
700MHz
PLL_SEL = 3.3V
3.2
-50
50
Test Conditions
Minimum
Typical
Maximum
700
4.2
150
25
25
±50
1
700
Units
MHz
ns
ps
ps
ps
ps
ms
ps
%
odc
Output Duty Cycle
47
53
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Phase jitter is dependent on the input source used.
NOTE 6: Characterized at VCO frequency of 622MHz.
8634BY
-01
www.icst.com/products/hiperclocks.html
4
REV. D APRIL 12, 2007
Integrated
Circuit
Systems, Inc.
ICS8634-01
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2V
V
CC
,
V
CCA
,
V
CCO
Qx
SCOPE
V
CC
LVPECL
V
EE
nQx
nCLK0,
nCLK1
V
CLK0,
CLK1
V
EE
PP
Cross Points
V
CMR
-1.3V ± 0.165V
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
nQ0:nQ4
nQx
Qx
Q0:Q4
t
cycle n
➤
➤
➤
t
cycle n+1
➤
nQy
Qy
tsk(o)
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
O
UTPUT
S
KEW
80%
V
SW I N G
Clock
Outputs
20%
t
R
t
F
20%
C
YCLE
-
TO
-C
YCLE
J
ITTER
nQ0:nQ4
80%
Q0:Q4
Pulse Width
t
PERIOD
odc =
t
PW
t
PERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/PU
LSE
W
IDTH
/P
ERIOD
nCLK0,
nCLK1
V
OH
V
OL
V
OH
V
OL
➤
t(Ø)
➤
nCLK0,
nCLK1
CLK0,
CLK1
nQ0:nQ4
Q0:Q4
t
PD
CLK0,
CLK1
nFB_IN
FB_IN
tjit(Ø)
=
t(Ø)
—
t(Ø)
mean
= Phase Jitter
t(Ø)
mean
= Static Phase Offset
(where
t(Ø)
is any random sample, and
t(Ø)
mean
is the average
of the sampled cycles measured on controlled edges)
P
ROPAGATION
D
ELAY
8634BY
-01
P
HASE
J
ITTER
& S
TATIC
P
HASE
O
FFSET
www.icst.com/products/hiperclocks.html
5
REV. D APRIL 12, 2007
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