IDT70V3569S4BFGI datasheet, PDF

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IDT70V3569S4BFGI: DescriptionDual-Port SRAM, 16KX36, 4.2ns, PBGA208, FINE PITCH, BGA-208; Categorystorage storage; File Size212KB，15 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT70V3569S4BFGI Overview

Dual-Port SRAM, 16KX36, 4.2ns, PBGA208, FINE PITCH, BGA-208

IDT70V3569S4BFGI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	208
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	4.2 ns
Other features	PIPELINED OUTPUT MODE; SELF TIMED WRITE CYCLE
JESD-30 code	S-PBGA-B208
JESD-609 code	e1
length	15 mm
memory density	589824 bit
Memory IC Type	DUAL-PORT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	208
word count	16384 words
character code	16000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	16KX36
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	15 mm
Base Number Matches	1

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HIGH-SPEED 3.3V 16K x 36

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V I/O

Features:

PRELIMINARY

IDT70V3569S

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

Commercial: 4.2/5/6ns (max.)

Pipelined output mode

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)

Fast 4.2ns clock to data out

1.8ns setup to clock and 0.7ns hold on all control, data, and

address inputs @ 133MHz

Data input, address, byte enable and control registers

Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

LVTTL- compatible, single 3.3V (±150mV) power supply for

core

LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)

power supply for I/Os

Industrial temperature range (-40°C to +85°C) is

available for selected speeds

Available in a 208-pin Plastic Quad Flatpack (PQFP) and

208-ball fine-pitch Ball Grid Array

Functional Block Diagram

R/W

B B

3 3

L R

2 1

R/W

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

16K x 36

MEMORY

ARRAY

I/O

- I/O

35L

Din_L

Din_R

I/O

- I/O

35R

CLK

13L

CNTRST

ADS

CNTEN

CLK

Counter/

Address

Reg.

13R

ADDR_L

ADDR_R

Counter/

Address

Reg.

CNTRST

ADS

CNTEN

4831 tbl 01

OCTOBER 1999

DSC 4831/6

IDT70V3569S4BFGI Related Products

	IDT70V3569S4BFGI	IDT70V3569S4DRGI	IDT70V3569S4BFI	IDT70V3569S4DRI
Description	Dual-Port SRAM, 16KX36, 4.2ns, PBGA208, FINE PITCH, BGA-208	Dual-Port SRAM, 16KX36, 4.2ns, PQFP208, PLASTIC, QFP-208	Dual-Port SRAM, 16KX36, 4.2ns, PBGA208, FINE PITCH, BGA-208	Dual-Port SRAM, 16KX36, 4.2ns, PQFP208, PLASTIC, QFP-208
Is it lead-free?	Lead free	Lead free	Contains lead	Contains lead
Is it Rohs certified?	conform to	conform to	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	BGA	QFP	BGA	QFP
package instruction	TFBGA,	FQFP,	TFBGA,	FQFP,
Contacts	208	208	208	208
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B
Maximum access time	4.2 ns	4.2 ns	4.2 ns	4.2 ns
Other features	PIPELINED OUTPUT MODE; SELF TIMED WRITE CYCLE	PIPELINED OUTPUT MODE; SELF TIMED WRITE CYCLE	PIPELINED OUTPUT MODE; SELF TIMED WRITE CYCLE	PIPELINED OUTPUT MODE; SELF TIMED WRITE CYCLE
JESD-30 code	S-PBGA-B208	S-PQFP-G208	S-PBGA-B208	S-PQFP-G208
JESD-609 code	e1	e3	e0	e0
length	15 mm	28 mm	15 mm	28 mm
memory density	589824 bit	589824 bit	589824 bit	589824 bit
Memory IC Type	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM
memory width	36	36	36	36
Humidity sensitivity level	3	3	3	3
Number of functions	1	1	1	1
Number of terminals	208	208	208	208
word count	16384 words	16384 words	16384 words	16384 words
character code	16000	16000	16000	16000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
organize	16KX36	16KX36	16KX36	16KX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	FQFP	TFBGA	FQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	FLATPACK, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	FLATPACK, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	225	225
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	4.1 mm	1.2 mm	4.1 mm
Maximum supply voltage (Vsup)	3.45 V	3.45 V	3.45 V	3.45 V
Minimum supply voltage (Vsup)	3.15 V	3.15 V	3.15 V	3.15 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	TIN SILVER COPPER	MATTE TIN	TIN LEAD	TIN LEAD
Terminal form	BALL	GULL WING	BALL	GULL WING
Terminal pitch	0.8 mm	0.5 mm	0.8 mm	0.5 mm
Terminal location	BOTTOM	QUAD	BOTTOM	QUAD
Maximum time at peak reflow temperature	30	30	20	20
width	15 mm	28 mm	15 mm	28 mm

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