74LVC573APWDC1321AU datasheet, PDF

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74LVC573APWDC1321AU: DescriptionLVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20; Categorylogic logic; File Size156KB，20 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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74LVC573APWDC1321AU Overview

LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20

74LVC573APWDC1321AU Parametric

Parameter Name	Attribute value
Maker	NXP
package instruction	4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20
Reach Compliance Code	unknown
Other features	BROADSIDE VERSION OF 373
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G20
length	6.5 mm
Logic integrated circuit type	BUS DRIVER
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)	9.5 ns
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	4.4 mm
Base Number Matches	1

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74LVC573A

Octal D-type transparent latch with 5 V tolerant

inputs/outputs; 3-state

Rev. 5 — 19 February 2013

Product data sheet

1. General description

The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type

inputs for each latch and 3-state true outputs for bus-oriented applications. A Latch

Enable (LE) input and an Output Enable (OE) input are common to all internal latches.

When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches

are transparent, that is, a latch output changes each time its corresponding D-input

changes. When LE is LOW, the latches store the information that was present at the

D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.

When OE is LOW, the contents of the eight latches are available at the outputs. When OE

is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does

not affect the state of the latches.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices as translators in

mixed 3.3 V or 5 V applications.

The 74LVC573A is functionally identical to the 74LVC373A, but has a different pin

arrangement.

2. Features and benefits



5 V tolerant inputs/outputs, for interfacing with 5 V logic

Supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Direct interface with TTL levels

High-impedance when V

= 0 V

Flow-through pinout architecture

Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Specified from

40 C

to +85

C

and

40 C

to +125

C

74LVC573APWDC1321AU Related Products

	74LVC573APWDC1321AU	935300601115	74LVC573ABQ	935273507115
Description	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PBCC20, 4.50 X 2.50 MM, 0.50 MM HEIGHT, 0.50 MM PITCH, PLASTIC, SOT1045-2, QFN-20	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PQCC20, 2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-764-1, DHVQFN-20	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PQCC20, 2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-764-1, DHVQFN-20
Maker	NXP	NXP	NXP	NXP
package instruction	4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20	HVBCC,	HVQCCN, LCC20,.1X.18,20	HVQCCN,
Reach Compliance Code	unknown	unknown	compliant	unknown
series	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PDSO-G20	R-PBCC-B20	R-PQCC-N20	R-PQCC-N20
length	6.5 mm	4.5 mm	4.5 mm	4.5 mm
Logic integrated circuit type	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER
Number of digits	8	8	8	8
Number of functions	1	1	1	1
Number of ports	2	2	2	2
Number of terminals	20	20	20	20
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	HVBCC	HVQCCN	HVQCCN
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
propagation delay (tpd)	9.5 ns	18.4 ns	9.5 ns	9.5 ns
Maximum seat height	1.1 mm	0.5 mm	1 mm	1 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	1.2 V	1.65 V	1.2 V	1.2 V
Nominal supply voltage (Vsup)	2.7 V	3.3 V	2.7 V	2.7 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal form	GULL WING	BUTT	NO LEAD	NO LEAD
Terminal pitch	0.65 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	DUAL	BOTTOM	QUAD	QUAD
width	4.4 mm	2.5 mm	2.5 mm	2.5 mm
Base Number Matches	1	1	1	-

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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