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74LVC573ADB,112

Description
74LVC573A - Octal D-type transparent latch with 5 V tolerantinputs/outputs;ttt3-state SSOP2 20-Pin
Categorylogic    logic   
File Size273KB,17 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
Download Datasheet Parametric View All

74LVC573ADB,112 Overview

74LVC573A - Octal D-type transparent latch with 5 V tolerantinputs/outputs;ttt3-state SSOP2 20-Pin

74LVC573ADB,112 Parametric

Parameter NameAttribute value
Brand NameNexperia
Is it Rohs certified?conform to
MakerNexperia
Parts packaging codeSSOP2
package instruction5.30 MM, PLASTIC, MO-150, SOT-339-1, SSOP-20
Contacts20
Manufacturer packaging codeSOT339-1
Reach Compliance Codecompliant
Samacsys Description74LVC573A - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state@en-us
Other featuresBROADSIDE VERSION OF 373
seriesLVC/LCX/Z
JESD-30 codeR-PDSO-G20
JESD-609 codee4
length7.2 mm
Logic integrated circuit typeBUS DRIVER
Humidity sensitivity level1
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)9.5 ns
Maximum seat height2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)1.2 V
Nominal supply voltage (Vsup)2.7 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width5.3 mm
Base Number Matches1
74LVC573A
Rev. 7 — 30 March 2020
Octal D-type transparent latch
with 5 V tolerant inputs/outputs; 3-state
Product data sheet
1. General description
The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type inputs for
each latch and 3-state true outputs for bus-oriented applications. A Latch Enable (LE) input and an
Output Enable (OE) input are common to all internal latches.
When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are
transparent, that is, a latch output changes each time its corresponding D-input changes. When
LE is LOW, the latches store the information that was present at the D-inputs one set-up time
preceding the HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH,
the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the
state of the latches.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied
to the outputs. These features allow the use of these devices as translators in mixed 3.3 V or 5 V
applications.
The 74LVC573A is functionally identical to the 74LVC373A, but has a different pin arrangement.
2. Features and benefits
5 V tolerant inputs/outputs, for interfacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when V
CC
= 0 V
Flow-through pinout architecture
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
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