5962-8983902RX datasheet, PDF - EEWORLD Datasheet

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5962-8983902RX: DescriptionEE PLD, 20ns, CMOS, CDIP20, CERDIP-20; CategoryProgrammable logic devices Programmable logic; File Size364KB，10 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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5962-8983902RX Overview

EE PLD, 20ns, CMOS, CDIP20, CERDIP-20

5962-8983902RX Parametric

Parameter Name	Attribute value
Maker	Lattice
Parts packaging code	DIP
package instruction	DIP,
Contacts	20
Reach Compliance Code	unknown
ECCN code	EAR99
Other features	1 EXTERNAL CLOCK; REGISTER PRELOAD
maximum clock frequency	33.3 MHz
JESD-30 code	R-GDIP-T20
length	25.27 mm
Dedicated input times	8
Number of I/O lines	8
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	8 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Programmable logic type	EE PLD
propagation delay	20 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm
Base Number Matches	1

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Description	EE PLD, 20ns, CMOS, CDIP20, CERDIP-20	EE PLD, 15ns, CMOS, CDIP20, CERDIP-20	EE PLD, 20ns, CMOS, CQCC20, LCC-20	EE PLD, 15ns, CMOS, CQCC20, LCC-20	EE PLD, 20ns, PAL-Type, CMOS, CDIP20, CERDIP-20	EE PLD, 20ns, PAL-Type, CMOS, CQCC20, LCC-20	EE PLD, 30ns, PAL-Type, CMOS, CDIP20, CERDIP-20
Parts packaging code	DIP	DIP	QLCC	QLCC	DIP	QLCC	DIP
package instruction	DIP,	DIP,	QCCN,	QCCN,	CERDIP-20	LCC-20	CERDIP-20
Contacts	20	20	20	20	20	20	20
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Other features	1 EXTERNAL CLOCK; REGISTER PRELOAD	1 EXTERNAL CLOCK; REGISTER PRELOAD	1 EXTERNAL CLOCK; REGISTER PRELOAD	1 EXTERNAL CLOCK; REGISTER PRELOAD	PAL WITH MACROCELLS; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET; SHARED INPUT/CLOCK	PAL WITH MACROCELLS; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET; SHARED INPUT/CLOCK	PAL WITH MACROCELLS; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET; SHARED INPUT/CLOCK
maximum clock frequency	33.3 MHz	41.6 MHz	33.3 MHz	41.6 MHz	33.3 MHz	33.3 MHz	22.2 MHz
JESD-30 code	R-GDIP-T20	R-GDIP-T20	S-CQCC-N20	S-CQCC-N20	R-GDIP-T20	S-CQCC-N20	R-GDIP-T20
length	25.27 mm	25.27 mm	8.89 mm	8.89 mm	25.27 mm	8.89 mm	25.27 mm
Dedicated input times	8	8	8	8	8	8	8
Number of I/O lines	8	8	8	8	8	8	8
Number of terminals	20	20	20	20	20	20	20
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
organize	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED
encapsulated code	DIP	DIP	QCCN	QCCN	DIP	QCCN	DIP
Package shape	RECTANGULAR	RECTANGULAR	SQUARE	SQUARE	RECTANGULAR	SQUARE	RECTANGULAR
Package form	IN-LINE	IN-LINE	CHIP CARRIER	CHIP CARRIER	IN-LINE	CHIP CARRIER	IN-LINE
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	20 ns	15 ns	20 ns	15 ns	20 ns	20 ns	30 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	5.08 mm	2.54 mm	2.54 mm	5.08 mm	2.54 mm	5.08 mm
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	YES	YES	NO	YES	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	THROUGH-HOLE	THROUGH-HOLE	NO LEAD	NO LEAD	THROUGH-HOLE	NO LEAD	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	1.27 mm	1.27 mm	2.54 mm	1.27 mm	2.54 mm
Terminal location	DUAL	DUAL	QUAD	QUAD	DUAL	QUAD	DUAL
width	7.62 mm	7.62 mm	8.89 mm	8.89 mm	7.62 mm	8.89 mm	7.62 mm
Base Number Matches	1	1	1	1	1	1	1

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