MAX 5000
®
Programmable Logic
Device Family
Data Sheet
May 1999, ver. 5
Features...
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Advanced Multiple Array MatriX (MAX
®
) 5000 architecture
combining speed and ease-of-use of PAL devices with the density of
programmable gate arrays
Complete family of high-performance, erasable CMOS EPROM
erasable programmable logic devices (EPLDs) for designs ranging
from fast 28-pin address decoders to 100-pin LSI custom peripherals
600 to 3,750 usable gates (see Table 1)
Fast, 15-ns combinatorial delays and 76.9-MHz counter frequencies
Configurable expander product-term distribution allowing more
than 32 product terms in a single macrocell
28 to 100 pins available in dual in-line package (DIP), J-lead chip
carrier, pin-grid array (PGA), and quad flat pack (QFP) packages
Programmable registers providing D, T, JK, and SR flipflop
functionality with individual clear, preset, and clock controls
Programmable security bit for protection of proprietary designs
Software design support featuring the Altera
®
MAX+PLUS
®
II
development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations
Table 1. MAX 5000 Device Features
Feature
Usable gates
Macrocells
Logic array blocks (LABs)
Expanders
Routing
Maximum user I/O pins
t
PD
(ns)
t
ASU
(ns)
t
CO
(ns)
f
CNT
(MHz)
EPM5032
600
32
1
64
Global
24
15
4
10
76.9
EPM5064
1,250
64
4
128
PIA
36
25
4
14
50
EPM5128
2,500
128
8
256
PIA
60
25
4
14
50
EPM5130
2,500
128
8
256
PIA
84
25
4
14
50
EPM5192
3,750
192
12
384
PIA
72
25
4
14
50
9
MAX 5000
Altera Corporation
A-DS-M5000-05
709
MAX 5000 Programmable Logic Device Family Data Sheet
...and More
Features
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Programming support with Altera’s Master Programming Unit
(MPU) or programming hardware from third-party manufacturers
Additional design entry and simulation support provided by EDIF,
library of parameterized modules (LPM), Verilog HDL, VHDL, and
other interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, and Viewlogic
General
Description
The MAX 5000 family combines innovative architecture and advanced
process technologies to offer optimum performance, flexibility, and the
highest logic-to-pin ratio of any general-purpose programmable logic
device (PLD) family. The MAX 5000 family provides 600 to 3,750 usable
gates, pin-to-pin delays as fast as 15 ns, and counter frequencies of up to
76.9 MHz (see Table 2).
Table 2. MAX 5000 Device Speed Grades
Device
15 ns
EPM5032
EPM5064
EPM5128
EPM5130
EPM5192
Speed (t
PD1
)
20 ns
v
25 ns
v
v
v
v
v
v
v
v
v
v
v
30 ns
35 ns
v
The MAX 5000 architecture supports 100% TTL emulation and
high-density integration of multiple SSI, MSI, and LSI logic functions. For
example, an EPM5192 device can replace over 100 74-series devices; it can
integrate complete subsystems into a single package, saving board area
and reducing power consumption. MAX 5000 EPLDs are available in a
wide range of packages (see Table 3), including the following:
s
s
s
s
Windowed ceramic and plastic dual in-line (CerDIP and PDIP)
Plastic J-lead chip carrier (PLCC)
Windowed ceramic pin-grid array (PGA)
Plastic quad flat pack (PQFP)
710
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Table 3. MAX 5000 Pin Count & Package Options
Device
CerDIP
EPM5032
EPM5064
EPM5128
EPM5130
EPM5192
28
Pin Count
PDIP
28
PLCC
28
44
68
84
84
PGA
PQFP
68
100
84
100
MAX 5000 EPLDs have between 32 and 192 macrocells that are combined
into groups called logic array blocks (LABs). Each macrocell has a
programmable-AND/fixed-OR array and a configurable register that
provides D, T, JK, or SR operation with independent programmable clock,
clear, and preset functions. To build complex logic functions, each
macrocell can be supplemented with shareable expander product terms
(“shared expanders”) to provide more than 32 product terms per
macrocell.
The MAX 5000 family is supported by Altera’s MAX+PLUS II
development system, a single, integrated package that offers schematic,
text—including the Altera Hardware Description Language (AHDL)—
and waveform design entry, compilation and logic synthesis, simulation
and timing analysis, and device programming. The MAX+PLUS II system
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry-standard PC- and UNIX workstation-based EDA tools. The
MAX+PLUS II software runs on Windows-based PCs as well as Sun
SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000
workstations.
9
MAX 5000
f
Functional
Description
For more information on the MAX+PLUS II development system, see the
MAX+PLUS II Programmable Logic Development System & Software Data
Sheet.
This section provides a functional description of MAX 5000 EPLDs, which
have the following architectural features:
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Logic array blocks
Macrocells
Clocking options
Expander product terms
Programmable interconnect array
I/O control blocks
Altera Corporation
711
MAX 5000 Programmable Logic Device Family Data Sheet
The MAX 5000 architecture is based on the concept of linking high-
performance, flexible logic array modules called LABs. Multiple LABs are
linked via the programmable interconnect array (PIA), a global bus that is
fed by all I/O pins and macrocells. In addition to these basic elements, the
MAX 5000 architecture includes 8 to 20 dedicated inputs, each of which
can be used as a high-speed, general-purpose input. Alternatively, one of
the dedicated inputs can be used as a high-speed global clock for registers.
Logic Array Blocks
MAX 5000 EPLDs contain 1 to 12 LABs. The EPM5032 has a single LAB,
while the EPM5064, EPM5128, EPM5130, and EPM5192 contain multiple
LABs. Each LAB consists of a macrocell array and an expander product-
term array (see Figure 1). The number of macrocells and expanders in the
arrays varies with each device.
Figure 1. MAX 5000 Architecture
8 to 20
Dedicated
Inputs
16
LAB A
LAB
Interconnect
PIA in
Multi-LAB
Devices Only
PIA
24
Macrocell
Array
I/O
Control
Block
Expander
Product-Term
Array
4 to 16
I/O Pins
per LAB
Feedback from
I/O Pins to LAB
(Single-LAB
Devices Only)
To All Other LABs
712
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Macrocells are the primary resource for logic implementation. Additional
logic capability is available from expanders, which can be used to
supplement the capabilities of any macrocell. The expander product-term
array consists of a group of unallocated, inverted product terms that can
be used and shared by all macrocells in the LAB to create combinatorial
and registered logic. These flexible macrocells and shareable expanders
facilitate variable product-term designs without the inflexibility of fixed
product-term architectures. All macrocell outputs are globally routed
within an LAB via the LAB interconnect. The outputs of the macrocells
also feed the I/O control block, which consists of groups of
programmable tri-state buffers and I/O pins. In the EPM5064, EPM5128,
EPM5130, and EPM5192 devices, multiple LABs are connected by a PIA.
All macrocells feed the PIA to provide efficient routing for high-fan-in
designs.
Macrocells
The MAX 5000 macrocell consists of a programmable logic array and an
independently configurable register (see Figure 2). The register can be
programmed to emulate D, T, JK, or SR operation, as a flow-through latch,
or bypassed for combinatorial operation. Combinatorial logic is
implemented in the programmable logic array, in which three product
terms that are
ORed
together feed one input to an
XOR
gate. The second
input to the
XOR
gate is used for complex
XOR
arithmetic logic functions
and for De Morgan’s inversion. The output of the
XOR
gate feeds the
programmable register or bypasses it for combinatorial operation.
9
MAX 5000
Altera Corporation
713
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