74AVCH20T245
20-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 4 — 14 December 2011
Product data sheet
1. General description
The 74AVCH20T245 is a 20-bit, dual supply transceiver that enables bi-directional voltage
level translation. The device can be used as two 10-bit transceivers or as a single 20-bit
transceiver. It features four 10-bit input-output ports (1An, 1Bn and 2An, 2Bn), two output
enable inputs (nOE), two direction inputs (nDIR) and dual supplies (V
CC(A)
and V
CC(B)
).
V
CC(A)
and V
CC(B)
can be independently supplied at any voltage between 0.8 V and 3.6 V
making the device suitable for bi-directional voltage level translation between any of the
low voltage nodes: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The 1An and 2An ports, nOE
and nDIR are referenced to V
CC(A)
, the 1Bn and 2Bn ports are referenced to V
CC(B)
. A
HIGH on a 1DIR allows transmission from 1An to 1Bn and a LOW on 1DIR allows
transmission from 1Bn to 1An. A HIGH on nOE causes the outputs to assume a HIGH
impedance OFF-state.
The device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at
GND level, all output ports will assume a high impedance OFF-state. The bus hold
circuitry on the powered-up side always stays active.
2. Features and benefits
Wide supply voltage range:
V
CC(A)
: 0.8 V to 3.6 V
V
CC(B)
: 0.8 V to 3.6 V
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
380 Mbit/s ( 1.8 V to 3.3 V translation)
260 Mbit/s ( 1.1 V to 3.3 V translation)
260 Mbit/s ( 1.1 V to 2.5 V translation)
NXP Semiconductors
74AVCH20T245
20-bit dual supply translating transceiver; 3-state
210 Mbit/s ( 1.1 V to 1.8 V translation)
120 Mbit/s ( 1.1 V to 1.5 V translation)
100 Mbit/s ( 1.1 V to 1.2 V translation)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AVCH20T245DGG
40 C
to +125
C
74AVCH20T245DGV
40 C
to +125
C
74AVCH20T245BX
40 C
to +125
C
TSSOP56
Description
Version
plastic thin shrink small outline package; 56 leads; SOT364-1
body width 6.1 mm
Type number
TSSOP56
[1]
plastic thin shrink small outline package; 56 leads; SOT481-2
body width 4.4 mm
HXQFN60U plastic thermal enhanced extremely thin quad flat
package; no leads; 60 terminals; UTLP based;
body 4
6
0.5 mm
SOT1134-1
[1]
Also known as TVSOP56.
4. Functional diagram
1DIR
1OE
2DIR
2OE
1A1
1B1
V
CC(A)
to other nine channels
V
CC(B)
2A1
2B1
V
CC(A)
to other nine channels
V
CC(B)
001aal240
Fig 1.
Logic diagram
74AVCH20T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 14 December 2011
2 of 28
NXP Semiconductors
74AVCH20T245
20-bit dual supply translating transceiver; 3-state
terminal A1
index area
74AVCH20T245
D1
A1
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
A9
A10
D2
D6
A11
A12
B8
A13
GND
(1)
B9
B10
A14
A15
D7
A16
B11
A18
A17
D3
B12
A19
B13
A20
B14
A21
B15
A22
B16
A23
B17
A24
A32
D5
A31
A30
A29
A28
A27
D8
D4
A26
A25
B20
B19
B18
001aao234
(1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to
GND.
Fig 4.
Pin configuration SOT1134-1 (HXQFN60U)
74AVCH20T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 14 December 2011
5 of 28
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