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74LVT245B
3.3 V octal transceiver with direction pin (3-state)
Rev. 02 — 8 May 2008
Product data sheet
1. General description
The 74LVT245B is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V.
This device is an octal transceiver featuring non-inverting 3-state bus compatible outputs
in both send and receive directions. The control function implementation minimizes
external timing requirements. The device features an output enable (OE) input for easy
cascading and a direction (DIR) input for direction control.
2. Features
I
I
I
I
I
I
I
3-state buffers
Octal bidirectional bus interface
Input and output interface capability to systems at 5 V supply
TTL input and output switching levels
Output capability: +64 mA/−32 mA
Latch-up protection exceeds 500 mA per JEDEC Std 17
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs
Live insertion/extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
I
I
I
I
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVT245BD
74LVT245BDB
−40 °C
to +85
°C
−40 °C
to +85
°C
SO20
SSOP20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1
Type number
74LVT245BPW
−40 °C
to +85
°C
74LVT245BBQ
−40 °C
to +85
°C
DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
NXP Semiconductors
74LVT245B
3.3 V octal transceiver with direction pin (3-state)
4. Functional diagram
DIR
OE
2
A0
B0
3
A1
B1
4
A2
B2
5
A3
B3
6
A4
B4
7
A5
4
B5
8
A6
6
B6
9
A7
8
B7
11
9
mna175
1
19
18
17
19
16
1
G3
3EN1
3EN2
15
2
14
3
1
2
18
17
16
15
14
13
12
11
13
5
12
7
mna174
Fig 1.
Logic diagram
Fig 2.
IEC logic symbol
74LVT245B_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 8 May 2008
2 of 15
NXP Semiconductors
74LVT245B
3.3 V octal transceiver with direction pin (3-state)
5. Pinning information
5.1 Pinning
74LVT245B
terminal 1
index area
A0
A1
DIR
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
20 V
CC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
001aah723
2
3
4
5
6
7
8
9
GND 10
B7 11
GND
(1)
20 V
CC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
A2
A3
A4
A5
A6
A7
74LVT245B
1
DIR
GND 10
001aah724
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 3.
Pin configuration for SO20 and (T)SSOP20
Fig 4.
Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
DIR
A0 to A7
GND
B0 to B7
OE
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
18, 17, 16, 15, 14, 13, 12, 11
19
20
Description
direction control
data input/output
ground (0 V)
data input/output
output enable input (active LOW)
supply voltage
74LVT245B_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 8 May 2008
3 of 15
NXP Semiconductors
74LVT245B
3.3 V octal transceiver with direction pin (3-state)
6. Functional description
Table 3.
Inputs
OE
L
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high impedance OFF-state.
Function selection
Inputs/outputs
DIR
L
H
X
An
An = Bn
inputs
Z
Bn
inputs
Bn = An
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
[1][2]
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
P
tot
[1]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
total power dissipation
Conditions
[3]
Min
−0.5
−0.5
−0.5
−50
−50
-
−64
−65
[2]
Max
+4.6
+7.0
+7.0
-
-
128
-
+150
150
500
Unit
V
V
V
mA
mA
mA
mA
°C
°C
mW
output in OFF or HIGH state
V
I
< 0
V
O
< 0
output in LOW state
output in HIGH state
[3]
-
-
T
amb
=
−40 °C
to +85
°C
[4]
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
°C.
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
For SO20 packages: above 70
°C
derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
°C
derate linearly with 4.5 mW/K.
[2]
[3]
[4]
74LVT245B_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 8 May 2008
4 of 15
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