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SN74LVC1G3157
SINGLE POLE, DOUBLE THROW ANALOG SWITCH
SCES424E − JANUARY 2003 - REVISED JUNE 2005
D
1.65-V to 5.5-V V
CC
Operation
D
Useful for Both Analog and Digital
D
D
D
D
Applications
Specified Break-Before-Make Switching
Rail-to-Rail Signal Handling
High Degree of Linearity
High Speed, Typically 0.5 ns
(V
CC
= 3 V, C
L
= 50 pF)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
D
Low On-State Resistance, Typically
≈6 Ω
D
D
(V
CC
= 4.5 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
DRL PACKAGE
(TOP VIEW)
YEP OR YZP PACKAGE
(BOTTOM VIEW)
B2
GND
B1
1
6
S
V
CC
A
B2
GND
1
2
3
6
5
4
S
V
CC
A
B2
GND
B1
1
2
3
6
5
4
S
V
CC
A
B1
GND
B2
3 4
2 5
1 6
A
V
CC
S
2
5
B1
3
4
See mechanical drawings for dimensions.
description/ordering information
This single-pole, double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes
of up to V
CC
(peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
TA
PACKAGE†
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SOT (SOT-23) − DBV
SOT (SC-70) − DCK
SOT (SOT-553) − DRL
Tape and reel
SN74LVC1G3157YZPR
Tape and reel
Tape and reel
Reel of 4000
SN74LVC1G3157DBVR
SN74LVC1G3157DCKR
SN74LVC1G3157DRLR
C5_
CC5_
ORDERABLE
PART NUMBER
SN74LVC1G3157YEPR
_ _ _C5_
TOP-SIDE
MARKING‡
−40°C to 85°C
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb,
•
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2005, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
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1
SN74LVC1G3157
SINGLE POLE, DOUBLE THROW ANALOG SWITCH
SCES424E − JANUARY 2003 - REVISED JUNE 2005
FUNCTION TABLE
CONTROL
INPUT
S
L
H
ON
CHANNEL
B1
B2
logic diagram (positive logic)
B2
1
6
S
4
A
B1
3
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Control input voltage range, V
IN
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Switch I/O voltage range, V
I/O
(see Notes 1, 2, 3, and 4) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Control input clamp current, I
IK
(V
IN
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/O port diode current, I
IOK
(V
I/O
< 0 or V
I/O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
On-state switch current, I
I/O
(V
I/O
= 0 to V
CC
) (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±128
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±100
mA
Package thermal impedance,
θ
JA
(see Note 6): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
DRL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 5.5 V maximum.
4. VI, VO, VA, and VBn are used to denote specific conditions for VI/O.
5. II, IO, IA, and IBn are used to denote specific conditions for II/O.
6. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SN74LVC1G3157
SINGLE POLE, DOUBLE THROW ANALOG SWITCH
SCES424E − JANUARY 2003 - REVISED JUNE 2005
recommended operating conditions (see Note 7)
MIN
VCC
VI/O
VIN
VIH
VIL
High-level input voltage, control input
Low-level input voltage, control input
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.65
0
0
VCC
×
0.75
VCC
×
0.7
VCC
×
0.25
VCC
×
0.3
20
20
10
10
ns/V
MAX
5.5
VCC
5.5
UNIT
V
V
V
V
V
∆t/∆v
Input transition rise/fall time
TA
−40
85
°C
NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
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3
SN74LVC1G3157
SINGLE POLE, DOUBLE THROW ANALOG SWITCH
SCES424E − JANUARY 2003 - REVISED JUNE 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VI = 0 V
VI = 1.65 V
VI = 0 V
VI = 2.3 V
VI = 0 V
VI = 3 V
VI = 0 V
VI = 2.4 V
VI = 4.5 V
On-state switch resistance
over signal range‡§
0
≤
VBn
≤
VCC
(see Figures 1 and 2)
IO= 4 mA
IO = −4 mA
IO = 8 mA
IO = −8 mA
IO = 24 mA
IO = −24 mA
IO = 30 mA
IO = −30 mA
IO = −30 mA
IA = −4 mA
IA = −8 mA
IA = −24 mA
IA = −30 mA
IA = −4 mA
IA = −8 mA
IA = −24 mA
IA = −30 mA
IA = −4 mA
IA = −8 mA
IA = −24 mA
IA = −30 mA
Ioff
k
IS(on)
IIN
ICC
∆I
CC
Cin
Cio(off)
Cio(on)
Off-state switch leakage current
On-state switch leakage current
Control input current
Supply current
Supply-current change
Control input
capacitance
Switch input/output
capacitance
Switch input/output
capacitance
S
Bn
Bn
A
0
≤
VI, VO
≤
VCC, (see Figure 3)
VI = VCC or GND,
VO = Open (see Figure 4)
0
≤
VIN
≤
VCC
VIN = VCC or GND
VIN = VCC − 0.6 V
VCC
1.65 V
2.3 V
3V
MIN
TYP†
11
15
8
11
7
9
6
4.5 V
1.65 V
2.3 V
3V
4.5 V
1.65 V
2.3 V
3V
4.5 V
1.65 V
2.3 V
3V
4.5 V
1.65 V
to 5.5 V
5.5 V
0 V to
5.5 V
5.5 V
5.5 V
5V
5V
5V
2.7
5.2
17.3
17.3
0.5
0.1
0.1
0.1
110
26
9
4
±0.05
±1
±1
†
±1
±0.1
†
±0.05
1
±1
±1
†
10
500
µA
A
A
µA
µA
A
µA
µA
pF
pF
pF
Ω
Ω
7
7
MAX
20
50
12
30
9
20
7
12
15
140
45
18
10
Ω
Ω
UNIT
ron
On-state switch resistance‡
See
Figures 1 and 2
rrange
∆r
on
Difference of on-state
resistance between switches‡¶#
See Figure 1
VBn = 1.15 V
VBn = 1.6V
VBn = 2.1 V
VBn = 3.15 V
ron(flat)
ON resistance flatness‡¶||
0
≤
VBn
≤
VCC
† TA = 25°C
‡ Measured by the voltage drop between I/O pins at the indicated current through the switch. ON resistance is determined by the lower of the
voltages on the two (A or B) ports.
§ Specified by design
¶
∆r
on = ron(max) − ron(min) measured at identical VCC, temperature, and voltage levels.
# This parameter is characterized, but not tested in production.
|| Flatness is defined as the difference between the maximum and minimum values of ON resistance over the specified range of conditions.
k
I is the same as I
off
S(off) (off-state switch leakage current).
4
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