810252BKI-02LFT datasheet, PDF

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810252BKI-02LFT: DescriptionPLL Based Clock Driver, 810252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32; Categorylogic logic; File Size4MB，19 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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810252BKI-02LFT Overview

PLL Based Clock Driver, 810252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32

810252BKI-02LFT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFN
package instruction	5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32
Contacts	32
Reach Compliance Code	compliant
ECCN code	EAR99
series	810252
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N32
JESD-609 code	e3
length	5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	32
Actual output times	2
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	5 mm
minfmax	312.5 MHz
Base Number Matches	1

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VCXO JITTER ATTENUATOR &

FEMTOCLOCK™ MULTIPLIER

ICS810252I-02

ENERAL

ESCRIPTION

The ICS810252I-02 is a member of the

HiPerClockS™

HiperClockS™ family of high performance clock

solutions from IDT. The ICS810252I-02 is a PLL

based synchronous multiplier that is optimized for

PDH or SONET to Ethernet clock jitter attenuation

and frequency translation. The device contains two internal

frequency multiplication stages that are cascaded in series.

The first stage is a VCXO PLL that is optimized to provide

reference clock jitter attenuation. The second stage is a

FemtoClock™ frequency multiplier that provides the low jitter,

high frequency Ethernet output clock that easily meets Gigabit

and 10 Gigabit Ethernet jitter requirements. Pre-divider and

output divider multiplication ratios are selected using device

selection control pins. The multiplication ratios are optimized

to support most common clock rates used in PDH, SONET

and Ethernet applications. The VCXO requires the use of an

external, inexpensive pullable crystal. The VCXO uses external

passive loop filter components which allows configuration of

the PLL loop bandwidth and damping characteristics. The

device is packaged in a space-saving 32-VFQFN package and

supports industrial temperature range.

EATURES

•

Two LVCMOS/LVTTL outputs, 14Ω output impedance

Each output supports independent frequency selection at

25MHz, 125MHz, 156.25MHz and 312.5MHz

•

Two differential inputs support the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

•

Accepts input frequencies from 8kHz to 155.52MHz including

8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,

125MHz and 155.52MHz

•

Attenuates the phase jitter of the input clock by using a low-

cost pullable fundamental mode VCXO crystal

•

VCXO PLL bandwidth can be optimized for jitter attenuation

and reference tracking

using external loop filter connection

•

FemtoClock frequency multiplier provides low jitter, high

frequency output

•

Absolute pull range: ±50ppm

•

FemtoClock VCO frequency: 625MHz

•

RMS phase jitter @ 125MHz, using a 25MHz crystal

(10kHz – 20MHz): 1.3ps

•

3.3V supply voltage

•

-40°C to 85°C ambient operating temperature

•

Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

SSIGNMENT

DDX

XTAL_OUT

32 31 30 29 28 27 26 25

LF1

LF0

ISET

GND

CLK_SEL

RESERVED

GND

9 10 11 12 13 14 15 16

PDSEL_2

PDSEL_1

PDSEL_0

DDA

ODBSEL_1

ODBSEL_0

ODASEL_1

ICS810252I-02

32-Lead VFQFN

5mm x 5mm x 0.925 package body

K Package

Top View

IDT

™

/ ICS

™

VCXO JITTER ATTENUATOR/MULTIPLIER

XTAL_IN

nCLK0

nCLK1

CLK0

CLK1

GND

DDO

GND

ODASEL_0

ICS810252BKI-02 REV. A

OCTOBER 22,2008

810252BKI-02LFT Related Products

	810252BKI-02LFT	810252BKI-02	810252BKI-02LF	810252BKI-02T
Description	PLL Based Clock Driver, 810252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32	PLL Based Clock Driver, 810252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32	PLL Based Clock Driver, 810252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32	PLL Based Clock Driver, 810252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32
Is it Rohs certified?	conform to	incompatible	conform to	incompatible
Parts packaging code	QFN	QFN	QFN	QFN
package instruction	5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32	HVQCCN,	5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32	HVQCCN,
Contacts	32	32	32	32
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99
series	810252	810252	810252	810252
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N32	S-XQCC-N32	S-XQCC-N32	S-XQCC-N32
JESD-609 code	e3	e0	e3	e0
length	5 mm	5 mm	5 mm	5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1	1	1
Number of terminals	32	32	32	32
Actual output times	2	2	2	2
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	225	260	225
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns	0.2 ns	0.2 ns	0.2 ns
Maximum seat height	1 mm	1 mm	1 mm	1 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	MATTE TIN	TIN LEAD	MATTE TIN	TIN LEAD
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30	30
width	5 mm	5 mm	5 mm	5 mm
minfmax	312.5 MHz	312.5 MHz	312.5 MHz	312.5 MHz
Base Number Matches	1	1	1	1
Maker	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)

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